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W132-10B PDF预览

W132-10B

更新时间: 2024-02-22 10:37:32
品牌 Logo 应用领域
其他 - ETC 时钟驱动器
页数 文件大小 规格书
13页 154K
描述
Ten Distributed-Output Clock Driver

W132-10B 技术参数

生命周期:Active零件包装代码:TSSOP
包装说明:TSSOP,针数:24
Reach Compliance Code:unknown风险等级:5.75
Is Samacsys:N系列:132
输入调节:STANDARDJESD-30 代码:R-PDSO-G24
长度:7.8 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
功能数量:1反相输出次数:
端子数量:24实输出次数:10
最高工作温度:70 °C最低工作温度:
输出特性:SERIES-RESISTOR封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH认证状态:COMMERCIAL
Same Edge Skew-Max(tskwd):0.1 ns座面最大高度:1.1 mm
最大供电电压 (Vsup):3.63 V最小供电电压 (Vsup):2.97 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
宽度:4.4 mm最小 fmax:140 MHz
Base Number Matches:1

W132-10B 数据手册

 浏览型号W132-10B的Datasheet PDF文件第7页浏览型号W132-10B的Datasheet PDF文件第8页浏览型号W132-10B的Datasheet PDF文件第9页浏览型号W132-10B的Datasheet PDF文件第11页浏览型号W132-10B的Datasheet PDF文件第12页浏览型号W132-10B的Datasheet PDF文件第13页 
W134M/W134S  
Table 14. Device Characteristics  
Parameter  
Description  
Min.  
Max.  
3.75  
60  
Unit  
ns  
tCYCLE  
tJ  
Clock Cycle Time  
Cycle-to-Cycle Jitter at Clk/ClkB[7]  
2.5  
-
ps  
Total Jitter over 2, 3, or 4 Clock Cycles[7]  
266-MHz Cycle-to-Cycle Jitter[8]  
266-MHz Total Jitter over 2, 3, or 4 Clock Cycles[8]  
-
100  
100  
160  
-
ps  
-
ps  
-
1
ps  
tSTEP  
Phase Aligner Phase Step Size (at Clk/ClkB)  
ps  
tERR,PD  
Phase Detector Phase Error for Distributed Loop Measured at PclkM-  
SynclkN (rising edges) (does not include clock jitter)  
100  
100  
ps  
tERR,SSC  
VX,STOP  
VX  
PLL Output Phase Error when Tracking SSC  
Output Voltage during Clk Stop (StopB=0)  
Differential Output Crossing-Point Voltage  
Output Voltage Swing (p-p single-ended)[9]  
Output High Voltage  
100  
1.1  
1.3  
0.4  
-
100  
2.0  
1.8  
0.6  
2.0  
-
ps  
V
V
VCOS  
VOH  
V
V
V
VOL  
Output Low voltage  
1.0  
12  
-
rOUT  
Output Dynamic Resistance (at pins)[10]  
Output Current during Hi-Z (S0 = 0, S1 = 1)  
Output Current during Clk Stop (StopB = 0)  
Output Duty Cycle over 10,000 Cycles  
Output Cycle-to-Cycle Duty Cycle Error  
Output Rise and Fall Times (measured at 20%80% of output voltage)  
50  
IOZ  
50  
µA  
IOZ,STOP  
DC  
tDC,ERR  
tR,tF  
-
500  
60  
µA  
40  
-
%tCYCLE  
ps  
50  
250  
-
500  
100  
ps  
tCR,CF  
Difference between Output Rise and Fall Times on the Same Pin of a  
ps  
Single Device (20%80%)  
Notes:  
7. Output Jitter spec measured at tCYCLE = 2.5 ns.  
8. Output Jitter Spec measured at tCYCLE = 3.75 ns.  
9.  
VCOS = VOHVOL.  
10. rOUT = VO/ IO. This is defined at the output pins.  
Ordering Information  
Package  
Ordering Code  
W134M/W134S  
Name  
Package Type  
H
24-pin SSOP (150 mils)  
Document #: 38-07426 Rev. *A  
Page 10 of 13  

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