Datasheet > W133H

W133H

更新时间： 2023-01-02 16:52:47

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		光电二极管
页数	文件大小	规格书
13页	147K
描述
Processor Specific Clock Generator, 133MHz, CMOS, PDSO56, 0.300 INCH, SSOP-56

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W133H 数据手册

PRELIMINARY

W133

Spread Spectrum System Frequency Synthesizer

CPU Output Jitter: ......................................................250 ps

Features

CPUdiv2 Output Jitter:.................................................250 ps

• Maximized EMI suppression using Cypress’s spread

spectrum technology

• Intel CK98 Specification compliant

• 0.5% downspread outputs deliver up to 10 dB lower EMI

• Four skew-controlled copies of CPU output

• EightcopiesofPCIoutput(synchronousw/CPUoutput)

• Four copies of 66-MHz fixed frequency 3.3V clock

• Two copies of CPU/2 outputs for synchronous memory

reference

48 MHz, 3V66, PCI, IOAPIC Output Jitter:..................500 ps

CPU0:3, CPUdiv2_ 0:1 Output Skew:.........................175 ps

PCI_F, PCI1:7 Output Skew:.......................................500 ps

3V66_0:3, IOAPIC0:2 Output Skew; ...........................250 ps

CPU to 3V66 Output Offset:............. 0.0–1.5 ns (CPU leads)

3V66 to PCI Output Offset:.............. 1.5–4.0 ns (3V66 leads)

CPU to IOAPIC Output Offset: ......... 1.5–4.0 ns (CPU leads)

• Three copies of 16.67-MHz IOAPIC clock, synchronous

to CPU clock

• One copy of 48-MHz USB output

• Two copies of 14.31818-MHz reference clock

• Programmable to 133- or 100-MHz operation

• Powermanagementcontrolpinsforclockstopandshut

down

Logic inputs, except SEL133/100#, have 250-kΩ pull-up

resistors.

Table 1. Pin Selectable Frequency^[1]

SEL133/100#

CPU0:3 (MHz)

133 MHz

PCI

33.3 MHz

100 MHz

• Available in 56-pin SSOP

Note:

1. See Table 2 for complete mode selection details.

Key Specifications

Supply Voltages:...................................... V_DDQ3= 3.3V±5%

V_DDQ2= 2.5V±5%

Block Diagram

Pin Configuration

GND

REF0

REF1

VDDQ3

GND

VDDQ2

IOAPIC2

IOAPIC1

IOAPIC0

GND

XTAL

OSC

REF0:1

CPU_STOP#

STOP

Clock

Logic

VDDQ2

CPU0:3

CPUdiv2_1

CPUdiv2_0

GND

VDDQ2

CPU3

CPU2

GND

VDDQ2

CPU1

CPU0

GND

VDDQ3

GND

PCI_F

PCI1

VDDQ3

PCI2

÷2

CPUdiv2_0:1

3V66_0:3

SPREAD#

SEL0

PCI3

GND

PLL 1

PCI4

SEL1

STOP

Clock

Logic

PCI5

SEL133/100#

÷2/÷1.5

VDDQ3

PCI6

PCI7

GND

PCI_F

PCI1:7

GND

PCI_STOP#

CPU_STOP#

PWRDWN#

SPREAD#

SEL1

3V66_0

3V66_1

VDDQ3

GND

STOP

Clock

Logic

÷2

PWRDWN#

PCI_STOP#

SEL0

3V66_2

VDDQ3

48MHz

GND

3V66_3

VDDQ3

SEL133/100#

Power

Down

Logic

÷2

IOAPIC0:2

Three-state

Logic

PLL2

48MHz

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-07166 Rev. *A

Revised December 15, 2002

12 3 4 5 6 7...13

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