VSP5620
VSP5621
VSP5622
www.ti.com
SBES022 –JULY 2011
16-Bit, 4-Channel, CCD/CMOS Sensor
Analog Front-End with LED Driver
Check for Samples: VSP5620, VSP5621, VSP5622
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FEATURES
23
•
Four-Channel CCD/CMOS Signal: 2-Channel,
•
Power (at 4-channel, LVDS, 3.3 V, without LED
Driver):
3-Channel, and 4-Channel Selectable
•
Power Supply: 3.3 V Only, Typ
(Built-in LDO, 3.3 V to 1.8 V)
Maximum Conversion Rate:
–
–
–
VSP5620: 320 mW at 35 MSPS
VSP5621: 406 mW at 50 MSPS
VSP5622: 523 mW at 70 MSPS
•
–
–
–
VSP5620: 35 MSPS
VSP5621: 50 MSPS
VSP5622: 70 MSPS
APPLICATIONS
•
•
•
Copiers
Facsimile Machines
Scanners
•
•
•
•
16-Bit Resolution
CDS/SH Selectable
Maximum Input Signal Range: 2.0 V
Analog and Digital Hybrid Gain:
DESCRIPTION
–
Analog Gain: 0.5 V/V to 3.5 V/V in
3/64-V/V Steps
Digital Gain: 1 V/V to 2 V/V in
1/256-V/V Steps
The
VSP5620/21/22
are
high-speed,
high-performance, 16-bit analog-to-digital-converters
(ADCs) that have four independent sampling circuit
channels for multi-output charge-coupled device
–
(CCD)
and
complementary
metal
oxide
•
•
Offset Correction DAC: ±250 mV, 8-Bit
Standard LVDS/CMOS Selectable Output:
–
semiconductor (CMOS) line sensors. Pixel data from
the sensor are sampled by the sample/hold (SH) or
correlated double sampler (CDS) circuit, and are then
converted to digital data by an ADC. Data output is
selectable in low-voltage differential signaling (LVDS)
or CMOS modes.
LVDS:
–
–
–
Data Channel: 2-Channel
Clock Channel: 1-Channel
8-Bit/7-Bit Serializer Selectable
The VSP5620/21/22 include a programmable gain to
support the pixel level inflection caused by luminance
and a built-in light-emitting diode (LED) driver to
–
CMOS: 4 Bits × 4
•
•
Timing Generator
–
–
Fast Transfer Clock: One Signal
Slow Transfer Clock: One Signal
adjust
the
brightness.
The
integrated
digital-to-analog-converter (DAC) can be used to
adjust the offset level for the analog input signal.
Furthermore, the timing generator (TG) is integrated
in these devices for the control of sensor operation.
LED Driver: Three Channels
–
Current: 60-mA/Channel Max,
16-Steps/Channel
•
•
Timing Adjustment Resolution: tMCLK/48
Input Clamp/Input Reference Level
Internal/External Selectable
The VSP5620/21/22 use 1.65 V to 1.95 V for the core
voltage and 3.0 V to 3.6 V for I/Os. The core voltage
is supplied by a built-in low-dropout regulator (LDO).
•
•
•
Reference DAC: 0.5 V, 1.1 V, 1.5 V, 2 V
SPI™: Three-Wire Serial
GPIO: Four-Port
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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3
SPI is a trademark of Motorola.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated