Datasheet > VSC9295XSM

VSC9295XSM

更新时间： 2024-02-11 03:50:28

品牌	Logo	应用领域
VITESSE		/
页数	文件大小	规格书
157页	1815K
描述
Telecom IC, PBGA1072,

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技术参数
数据手册

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VSC9295XSM 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.83	JESD-30 代码：	S-PBGA-B1072
端子数量：	1072	封装主体材料：	PLASTIC/EPOXY
封装代码：	BGA	封装等效代码：	BGA1072,34X34,50
封装形状：	SQUARE	封装形式：	GRID ARRAY
电源：	1.2,1.8/2.5,2.5/3.3 V	认证状态：	Not Qualified
子类别：	Other Telecom ICs	最大压摆率：	11000 mA
表面贴装：	YES	端子形式：	BALL
端子节距：	1.27 mm	端子位置：	BOTTOM

VSC9295XSM 数据手册

VSC9295

Datasheet

6.2

Thermal Specifications

Thermal specifications for this device are based on the JEDEC standard EIA/JESD51-2 and have been modeled

using a four-layer test board with two signal layers, a power plane, and a ground plane (2s2p PCB). For more

information, see the JEDEC standard.

Table 69. Thermal Resistances

_JA(°C/W) vs. Airflow (ft/min)

Part Order Number

θ_JC

100

200

VSC9295SM

0.22

10.4

5.5

VSC9295XSM

To achieve results similar to the modeled thermal resistance measurements, the guidelines for board design

described in the JEDEC standard EIA/JESD51 series must be applied. For information about specific

applications, see the following:

EIA/JESD51-5, Extension of Thermal Test Board Standards for Packages with Direct Thermal Attachment

Mechanisms

EIA/JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

EIA/JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements

EIA/JESD51-10, Test Boards for Through-Hole Perimeter Leaded Package Thermal Measurements

EIA/JESD51-11, Test Boards for Through-Hole Area Array Leaded Package Thermal Measurements

6.3

Moisture Sensitivity

This device is rated moisture sensitivity level 4 as specified in the joint IPC and JEDEC standard IPC/JEDEC

J-STD-020. For more information, see the IPC and JEDEC standard.

155 of 157

VMDS-10144 Revision 4.4

April 2009

1...152 153 154155156 157

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