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VSC852TP PDF预览

VSC852TP

更新时间: 2024-10-28 19:45:51
品牌 Logo 应用领域
VITESSE 电信电信集成电路
页数 文件大小 规格书
16页 643K
描述
Digital Time Switch, PBGA440, 35 X 35 MM, BGA-440

VSC852TP 技术参数

生命周期:Transferred零件包装代码:BGA
包装说明:BGA,针数:440
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.61JESD-30 代码:S-PBGA-B440
长度:35 mm功能数量:1
端子数量:440最高工作温度:85 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装形状:SQUARE
封装形式:GRID ARRAY认证状态:Not Qualified
座面最大高度:2.65 mm标称供电电压:3.3 V
表面贴装:YES电信集成电路类型:DIGITAL TIME SWITCH
温度等级:OTHER端子形式:BALL
端子节距:1.27 mm端子位置:BOTTOM
宽度:35 mmBase Number Matches:1

VSC852TP 数据手册

 浏览型号VSC852TP的Datasheet PDF文件第1页浏览型号VSC852TP的Datasheet PDF文件第2页浏览型号VSC852TP的Datasheet PDF文件第4页浏览型号VSC852TP的Datasheet PDF文件第5页浏览型号VSC852TP的Datasheet PDF文件第6页浏览型号VSC852TP的Datasheet PDF文件第7页 
VITESSE  
SEMICONDUCTOR CORPORATION  
Data Sheet  
1.6Gb/s 64x64  
Crosspoint Switch  
VSC852  
switch slice should connect to. The format of the program data is simple binary, where the binary value maps  
directly to the switch slice position and/or input port number. For example, program data 0000100/010110  
would direct output channel Y4 to connect to input channel A22.  
To program the switch core, the address and data (13 bits total) for the given output port must be serially  
clocked into the SDIN input. The LOAD pin must be asserted with the last serial program bit to load the pro-  
gram data into the on-chip program register. The program data will be held in the register until it is either repro-  
grammed or the chip is powered off. The last step to programming the switch core is to transfer the program  
data to the registers that control the state of each switch slice. The transfer is completed by asserting the CON-  
FIG pin. The CONFIG pin can be used as a strobe to allow multiple program commands to be implemented  
simultaneously. The CONFIG pin can also be tied HIGH (always asserted) so the core will reprogram after  
every LOAD pulse. See Figure 1.  
To read the current programming of the switch core, the desired address to query must be clocked into the  
chip’s SDIN port. The format of the program data is the same as for writing. Because of the depth of the on-chip  
registers, the address bits must be followed by another 6 CLK cycles so the address data is correctly positioned  
in the internal register. The dummy bits that are clocked in during the last 6 bits of the program data will be  
overwritten when READ is asserted. As the last dummy bit is clocked in, the READ pin must be asserted to  
load the on-chip program data into the shift register used for the serial interface logic. See Figure 2.  
Figure 1: Write Sequence Timing  
Figure 2: Read Sequence Timing  
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012  
G52245-0, Rev 4.1  
9/26/00  
Page 3  
Tel: (800)-VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com  
Internet: www.vitesse.com  

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