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VSC8164QR PDF预览

VSC8164QR

更新时间: 2024-02-15 05:28:43
品牌 Logo 应用领域
VITESSE /
页数 文件大小 规格书
16页 156K
描述
2.488 Gbit/sec to 2.7Gbit/sec 1:16 SONET/SDH Demux

VSC8164QR 技术参数

生命周期:Obsolete零件包装代码:QFP
包装说明:HFQFP,针数:128
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.84应用程序:SONET;SDH
JESD-30 代码:R-PQFP-G128长度:20 mm
功能数量:1端子数量:128
封装主体材料:PLASTIC/EPOXY封装代码:HFQFP
封装形状:RECTANGULAR封装形式:FLATPACK, HEAT SINK/SLUG, FINE PITCH
认证状态:Not Qualified座面最大高度:2.35 mm
标称供电电压:3.3 V表面贴装:YES
电信集成电路类型:ATM/SONET/SDH MUX/DEMUX端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
宽度:14 mmBase Number Matches:1

VSC8164QR 数据手册

 浏览型号VSC8164QR的Datasheet PDF文件第1页浏览型号VSC8164QR的Datasheet PDF文件第2页浏览型号VSC8164QR的Datasheet PDF文件第3页浏览型号VSC8164QR的Datasheet PDF文件第5页浏览型号VSC8164QR的Datasheet PDF文件第6页浏览型号VSC8164QR的Datasheet PDF文件第7页 
VITESSE  
SEMICONDUCTOR CORPORATION  
Preliminary Datasheet  
2.488 Gbit/sec to 2.7Gbit/sec  
1:16 SONET/SDH Demux  
VSC8164  
Decoupling of the power supplies is a critical element in maintaining the proper operation of the part. It is  
recommended that the V power supply be decoupled using a 0.1µF and 0.01µF capacitor placed in parallel  
CC  
on each V power supply pin as close to the package as possible. If room permits, a 0.001µF capacitor should  
CC  
also be placed in parallel with the 0.1µF and 0.01µF capacitors mentioned above. Recommended capacitors are  
low inductance ceramic SMT X7R devices. For the 0.1µF capacitor, a 0603 package should be used. The  
0.01µF and 0.001µF capacitors can be either 0603 or 0402 packages.  
For low frequency decoupling, 47µF tantalum low inductance SMT caps should be sprinkled over the  
boards main +3.3V power supply and placed close to the C-L-C pi filter.  
If the device is being used in an ECL environment with a -3.3V supply, then all references to decoupling  
V
must be changed to V , and all references to decoupling 3.3V must be changed to -3.3V.  
EE  
CC  
AC Characteristics  
Figure 5: AC Timing Waveforms  
CLK16O+  
Parallel data clock output  
tpdd  
D(0...15)+  
VALID DATA (1)  
VALID DATA (2)  
Parallel data outputs  
CLK32O+  
tpd32  
Parallel data clock output  
Figure 6: High Speed Input Timing  
DI+  
D1 D2  
D4 D5 D6 D7 D8 D9 D10D11 D12 D13D14 D15  
D3  
D0  
High speed differential serial data input  
HSCLKI+  
High speed differential clock input  
tdsu  
tdh  
Page 4  
VITESSE SEMICONDUCTOR CORPORATION  
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896  
G52239-0, Rev. 3.3  
5/17/00  

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