Datasheet > VSC8164QR

VSC8164QR

更新时间： 2024-01-22 02:51:34

品牌	Logo	应用领域
VITESSE		/
页数	文件大小	规格书
16页	156K
描述
2.488 Gbit/sec to 2.7Gbit/sec 1:16 SONET/SDH Demux

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VSC8164QR 技术参数

生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	HFQFP,	针数：	128
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.84	应用程序：	SONET;SDH
JESD-30 代码：	R-PQFP-G128	长度：	20 mm
功能数量：	1	端子数量：	128
封装主体材料：	PLASTIC/EPOXY	封装代码：	HFQFP
封装形状：	RECTANGULAR	封装形式：	FLATPACK, HEAT SINK/SLUG, FINE PITCH
认证状态：	Not Qualified	座面最大高度：	2.35 mm
标称供电电压：	3.3 V	表面贴装：	YES
电信集成电路类型：	ATM/SONET/SDH MUX/DEMUX	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
宽度：	14 mm	Base Number Matches：	1

VSC8164QR 数据手册

VITESSE

SEMICONDUCTOR CORPORATION

reliminary Datasheet

2.488 Gbit/sec to 2.7Gbit/sec

1:16 SONET/SDH Demux

SC8164

High Speed Interface

The incoming 2.488Gb/s data (up to 2.7Gb/s for FEC applications) and input clock are received by high

speed inputs DI and HSCLKI. The data and clock inputs are internally terminated by a center-tapped resistor

network. For differential input DC coupling, the network is terminated to the appropriate termination voltage

V_Term(pins HSDREF, HSCLKREF) providing a 50Ω to V_Termtermination for both true and complement inputs.

For differential input AC coupling, the network is terminated to V_Termvia a blocking capacitor.

In most situations these inputs will have high transition density and little DC offset. However, in cases

where this does not hold, direct DC connection is possible. All serial data and clock inputs have the same circuit

topology, as shown in Figure 4. The reference voltage is created by a resistor divider as shown. If the input sig-

nal is driven differentially and DC-coupled to the part, the mid-point of the input signal swing should be cen-

tered about this reference voltage and not exceed the maximum allowable amplitude (∆V_CMI, ∆V_IHSDC). For

single-ended, DC-coupling operations, it is recommended that the user provides an external reference voltage

which has better temperature and power supply noise rejection than the on-chip resistor divider. The external

reference should have a nominal value equivalent to the common mode switch point of the DC coupled signal,

and can be connected to either side of the differential gate.

Figure 4: High Speed Serial Clock and Data Inputs

Chip Boundary

V_CC= 3.3V

Z_O

C_IN

50Ω

C_AC

V_Term

50Ω

C_IN

Z_O

V_EE= 0V

_INTYP = 100 nF

C_ACTYP = 100 nF

Supplies

This device is specified as a LVPECL device with a single positive 3.3V supply. Should the user desire to

use the device in a ECL environment with a negative 3.3V supply, then VCC will be ground and VEE will be -

3.3V.

G52239-0, Rev. 3.3

5/17/00

VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

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