Datasheet > VSC8174QQ

VSC8174QQ

更新时间： 2024-02-23 02:25:33

品牌	Logo	应用领域
美高森美 - MICROSEMI		ATM 异步传输模式电信电信集成电路
页数	文件大小	规格书
2页	28K
描述
Mux/Demux, 1-Func, PQFP100, 14 X 14 MM, THERMALLY ENHANCED, PLASTIC, QFP-100

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技术参数
数据手册

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VSC8174QQ 技术参数

生命周期：	Transferred	零件包装代码：	QFP
包装说明：	HFQFP,	针数：	100
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.82	JESD-30 代码：	S-PQFP-G100
长度：	14 mm	功能数量：	1
端子数量：	100	封装主体材料：	PLASTIC/EPOXY
封装代码：	HFQFP	封装形状：	SQUARE
封装形式：	FLATPACK, HEAT SINK/SLUG, FINE PITCH	认证状态：	Not Qualified
座面最大高度：	2.35 mm	标称供电电压：	3.3 V
表面贴装：	YES	电信集成电路类型：	ATM/SONET/SDH MUX/DEMUX
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	QUAD	宽度：	14 mm
Base Number Matches：	1

VSC8174QQ 数据手册

VITESSE

SEMICONDUCTOR CORPORATION

Product Brief

9.953 Gbit/sec SONET/SDH

1:16 Demultiplexer withh Clock Generator

VSC8174

Features

• Data Polarity Invert

• 10 Gbit/sec SONET/SDH 1:16 Demux

• Bit Order Swap

• Integrated Clock and Data Recovery

• Input Data Sensitivity of 50mV

• Input Threshold Voltage Adjustment

• Operation at 9.953 to 10.66 Gb/s rates

• Low Speed LVDS Outputs

• High Speed 9.9 to 10.7 Ghz Clock Output

• Parity Bit Calculation

• Low Power Dissipation

• Single +3.3V Supply

• Meets SONET OC-192 and SDH STM-64 Jitter

Tolerance Requirements

• 19.44/20.83 Ref Clock Input

• Lock Error Detect, Lock to REFCLK

General Description

The VSC8174 combines a clock recovery unit and data retiming with a 1:16 demultiplexer on a single chip

to directly generate 16-bit wide data from an incoming 9.953/10.66 Gb/s data stream. An on-chip Phase Locked

Loop (PLL) with voltage controlled oscillator generates a 9.953/10.66 GHz clock, which remains phase locked

to the incoming data. The clock generator requires a 19.44/20.83 MHz PECL reference clock input (REFCK+).

The incoming data is retimed and demultiplexed into 16 parallel outputs. In addition, the input sampling point

can be adjusted in voltage for optimal data recovery. The device has two output alarm conditions: Loss of Lock

(LOL) reflects the lock condition of the PLL, no reference (NOREF) indicates the loss of reference clock input.

A parity bit is clocked out with the 16 parallel data. The device is packaged in a 100 pin thermally enhanced

Quad Flat Pack (QFP) and a 96 ball, Ball Grid Array (BGA).

VSC8174 Block Diagram

9.953

10.7 Gb/s

Data

and

Parity

Clock

Recovery

Data Re-timing

Data Stream

Processing

Optical

Electronics

Demux

Data Clock

622/666 MHz

Timing

Generation

G52315-0, Rev. 1.0

5/11/00

VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

Page 1

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