Datasheet > VSC8223XRV

VSC8223XRV

更新时间： 2024-01-16 20:49:07

品牌	Logo	应用领域
美高森美 - MICROSEMI		ATM 异步传输模式电信电信集成电路
页数	文件大小	规格书
26页	489K
描述
ATM/SONET/SDH Clock Recovery Circuit, CMOS, PQFP48,

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VSC8223XRV 技术参数

是否Rohs认证：	符合	生命周期：	Transferred
包装说明：	QFP, QFP48,.35SQ,20	Reach Compliance Code：	unknown
风险等级：	5.82	JESD-30 代码：	S-PQFP-G48
端子数量：	48	最高工作温度：	85 °C
最低工作温度：	-20 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	QFP	封装等效代码：	QFP48,.35SQ,20
封装形状：	SQUARE	封装形式：	FLATPACK
电源：	2.5 V	认证状态：	Not Qualified
子类别：	ATM/SONET/SDH ICs	最大压摆率：	217 mA
标称供电电压：	2.5 V	表面贴装：	YES
技术：	CMOS	电信集成电路类型：	ATM/SONET/SDH CLOCK RECOVERY CIRCUIT
温度等级：	OTHER	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
Base Number Matches：	1

VSC8223XRV 数据手册

VSC8223

Datasheet

Extended Multirate STS-12/STM-4, STS-3/STM-1 and FEC Clock and Data Recovery IC

● On-die input and output termination

FEATURES

● Selectable high-speed clock output

● Extended multirate clock and data recovery

support for STS-12/STM-4, STS-3/STM-1, and

FEC data rates

● Selectable LVPECL reference frequencies:

19.44 MHz, 77.76 MHz, or 155.52 MHz (or FEC)

● Internal phase-locked loop maintains clock

● Complies with Bellcore and ITU-T specifications

output in the absence of data

for jitter tolerance, transfer, and generation

● Low power CMOS technology

● 2.5 V supply operation

● Status indication signals (LVTTL) for:

Loss of signal (LOS)

Loss of lock (LOL)

No reference (NOREF)

● 0.4 W typical power dissipation

● 48-pin LQFP package

● Automatic and manual lock-to-reference modes

GENERAL DESCRIPTION

The VSC8223 device is a high-performance, extended multirate clock and data recovery (CDR) IC that supports

SONET/SDH systems operating at STS-12/STM-4, STS-3/STM-1, and forward error correction (FEC) data rates.

The VSC8223 generates a differential bit clock and differential retimed data.

High-speed input and output signals are terminated on-chip to maintain the highest degree of signal integrity possible.

Two selectable, externally supplied reference clock (REFCLK[1:0]) inputs support the phase-locked loop (PLL)

operation and are used to maintain a lock condition when the high-speed data is missing at the input. A reference

clock selector (RCLK_SEL) input allows the user to select between either of the two REFCLK inputs. The reference

clock frequency (155.52 MHz, 77.76 MHz, 19.44 MHz or FEC) to the VSC8223 is selected using the

RCLK_FSEL[1:0] control signals.

The loss of lock (LOL) status signal indicates the loss of lock of the PLL. The loss of signal (LOS) status signal

indicates the occurrence of an all zeros or all ones pattern. During a LOS condition, an all zeros data pattern is output

along with a SONET/SDH-quality clock (for SONET/SDH rates only).

During LOS conditions, the PLL automatically switches to the REFCLK. The PLL automatically switches back to the

high-speed input when the LOS signal is de-asserted. The PLL can also be manually forced into the lock to REFCLK

mode using the LREF control pin. In addition, the automatic lock to REFCLK mode can be disabled.

The VSC8223 device is available in a plastic, low-profile quad flat package (LQFP) with an exposed pad and a

7 mm × 7 mm body. The device is also available in a lead(Pb)-free package, VSC8223XRV.

G52417 Revision 4.0

July 2007

Tel: (800) VITESSE • FAX: (805) 987-5896 • E-mail: webmaster@vitesse.com

Internet: www.vitesse.com

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