Datasheet > VS1053B-L

VS1053B-L

更新时间： 2024-11-25 07:08:03

品牌	Logo	应用领域
其他 - ETC		/
页数	文件大小	规格书
82页	792K
描述
音频编解码芯片

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中文翻译

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数据手册

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VS1053B-L 数据手册

VS1053b Datasheet

VS1053b -

Ogg Vorbis/MP3/AAC/WMA/FLAC/

MIDI AUDIO CODEC CIRCUIT

Features

Description

VS1053b is an Ogg Vorbis/MP3/AAC/WMA/

FLAC/WAVMIDI audio decoder as well as an

PCM/IMA ADPCM/Ogg Vorbis encoder on a

single chip. It contains a high-performance,

proprietary low-power DSP processor core

VS_DSP⁴, data memory, 16 KiB instruction

RAM and 0.5+ KiB data RAM for user appli-

cations running simultaneously with any built-

in decoder, serial control and input data in-

terfaces, upto 8 general purpose I/O pins, an

UART, as well as a high-quality variable-sample-

rate stereo ADC (mic, line, line + mic or 2×line)

and stereo DAC, followed by an earphone am-

pliﬁer and a common voltage buffer.

• Decodes

Ogg Vorbis;

MP3 = MPEG 1 & 2 audio layer III (CBR

+VBR +ABR);

MP1/MP2 = layers I & II optional;

MPEG4 / 2 AAC-LC(+PNS),

HE-AAC v2 (Level 3) (SBR + PS);

WMA 4.0/4.1/7/8/9 all proﬁles (5-384 kbps);

General MIDI 1 / SP-MIDI format 0 ﬁles;

FLAC with software plugin;

WAV (PCM + IMA ADPCM)

• Encodes Ogg Vorbis w/ software plugin

• Encodes stereo IMA ADPCM / PCM

• Streaming support for MP3 and WAV

• EarSpeaker Spatial Processing

• Bass and treble controls

VS1053b receives its input bitstream through

a serial input bus, which it listens to as a

system slave. The input stream is decoded

and passed through a digital volume control

to an 18-bit oversampling, multi-bit, sigma-

delta DAC. The decoding is controlled via a

serial control bus. In addition to the basic de-

coding, it is possible to add application spe-

ciﬁc features, like DSP effects, to the user

RAM memory.

• Operates with a single 12..13 MHz clock

• Can also be used with a 24..26 MHz clock

• Internal PLL clock multiplier

• Low-power operation

• High-quality on-chip stereo DAC with no

phase error between channels

• Zero-cross detection for smooth volume

change

• Stereo earphone driver capable of driv-

Optional factory-programmable unique chip

ID provides basis for digital rights manage-

ment or unit identiﬁcation features.

ing a 30 Ω load

• Quiet power-on and power-off

• I2S interface for external DAC

• Separate voltages for analog, digital, I/O

• On-chip RAM for user code and data

• Serial control and data interfaces

• Can be used as a slave co-processor

• SPI ﬂash boot for special applications

• UART for debugging purposes

• New functions may be added with soft-

ware and upto 8 GPIO pins

• Lead-free RoHS-compliant package (Green)

Version: 1.13, 2011-05-27

12 3 4 5 6 7...82

中文翻译

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