Datasheet > VP520

VP520

更新时间： 2024-11-24 22:15:35

品牌	Logo	应用领域
MITEL		转换器商用集成电路
页数	文件大小	规格书
16页	165K
描述
PAL/NTSC to CIF/QCIF Converter

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中文翻译

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数据手册

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VP520 数据手册

VP520S

PAL/NTSC to CIF/QCIF Converter

Advance Information

Supersedes version in June 1995 Digital Video & DSP IC Handbook, HB3923-2

DS3504 - 3.2 October 1996

FEATURES

DESCRIPTION

■

Lower Power, pin compatible replacement for VP520

The VP520S is designed to convert 16 bit multiplexed

luminanceandchrominancedatabetweenCCIR601andCIF/

QCIF resolutions. Vertical and horizontal FIR filters are pro-

vided, with the vertical filters supported by on chip line stores.

The coefficients used by the filters are user definable, and are

down loaded from an independent host data bus. An internal

address generator supports an external DRAM frame store,

and also provides line to macroblock conversion.

When producing CIF or QCIF video the horizontal filters

precede the vertical filters, and are provided with between 8

and 16 taps. The vertical filters are provided with four CIF line

delays which allow a 5 tap filter to be implemented. When

producing QCIF the available RAM is used to provide six line

delays, which thus allows 7 tap filters to be used.

When the device is producing CCIR601 video, the incom-

ing data must be in macroblock format, and the vertical filters

precede the horizontal filters The inputs are firstly written to a

externalCIFsizedframestore, and arereadoutinlineformat.

The VP520S will support two complete frame stores, and

allows the CIF/QCIF data to be read out twice in order to

produce two interlaced fields of video.

The VP520S supports the conversion between CIF/QCIF

and NTSC video. An extra line is produced for every five lines

when producing CIF data, and one line in six is removed when

producing NTSC video. Poly phase filters are used to provide

the correct decimation and interpolation ratios.

Converts CCIR601 luminance and chrominance to CIF

or QCIF resolution, and vice versa, using a 27MHz

system clock.

■

Luminance and chrominance channels have their own

sets of horizontal and vertical filters with on chip line

stores

Each filter set may be configured to either decimate or

interpolate.

■

NTSC line insertion or removal mode

Produces / expects CIF/QCIF data in macroblock for-

mat.

■

120 Pin QFP Package

ASSOCIATED PRODUCTS

■

VP510 Colour Space Converter

VP2611 H261 Encoder

VP2615 H261 Decoder

VP2612 Video Multiplexer

VP2614 Video Demultiplexer

VP520S

FILTER BLOCK

Horizontal

Filters

MACROBLOCK

STROBE

COEFF

HOST

STORE

BUS

REQ BLKS

8 BIT

MACROBLOCK

BUS

INPUT/

OUTPUT

FIFO

8 BIT

LUMINANCE

FOUR

LINE

DELAYS

Vertical

Filters

16 BIT

FRAME STORE

BUS

FRAME START

/ READY

MUX

RAM ADDRESS

ADDRESS

FILTER BLOCK

GENERATOR

SUPPORTING

LINE TO BLOCK

CONVERSION

8 BIT

CHROMINANCE

CONTROL

MUXING

CREF

HREF

VREF

SYNC

GENERATOR

Fig 1 : Simplified Block Diagram

12 3 4 5 6 7...16

中文翻译

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与VP520相关器件

型号	品牌	获取价格	描述	数据表
VP5206ND	MICROCHIP	获取价格	VP5206ND
VP5206NW	MICROCHIP	获取价格	VP5206NW
VP520CGGGWR	ETC	获取价格	Video Converter Circuit
VP520CGGH1R	ETC	获取价格	Video Converter Circuit
VP520S	MITEL	获取价格	PAL/NTSC to CIF/QCIF Converter
VP520S/CG/GH1R	MICROSEMI	获取价格	Consumer Circuit, PQFP120, PLASTIC, QFP-120
VP520S/CG/GH1R	ZARLINK	获取价格	Consumer Circuit, PQFP120, PLASTIC, QFP-120
VP520SCG	MITEL	获取价格	PAL/NTSC to CIF/QCIF Converter
VP520SCGGH1R	MITEL	获取价格	PAL/NTSC to CIF/QCIF Converter
VP5225	SUPERTEX	获取价格	P-Channel Enhancement-Mode Vertical DMOS FET

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