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VP5225K4 PDF预览

VP5225K4

更新时间: 2024-11-25 03:19:15
品牌 Logo 应用领域
超科 - SUPERTEX 晶体晶体管功率场效应晶体管开关脉冲
页数 文件大小 规格书
3页 665K
描述
P-Channel Enhancement-Mode Vertical DMOS FET

VP5225K4 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TO-252AA包装说明:SMALL OUTLINE, R-PSSO-G2
针数:3Reach Compliance Code:unknown
ECCN代码:EAR99风险等级:5.92
Is Samacsys:N其他特性:LOGIC LEVEL COMPATIBLE
配置:SINGLE WITH BUILT-IN DIODE最小漏源击穿电压:250 V
最大漏极电流 (ID):0.645 A最大漏源导通电阻:3 Ω
FET 技术:METAL-OXIDE SEMICONDUCTORJEDEC-95代码:TO-252AA
JESD-30 代码:R-PSSO-G2JESD-609代码:e0
元件数量:1端子数量:2
工作模式:ENHANCEMENT MODE封装主体材料:PLASTIC/EPOXY
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED极性/信道类型:P-CHANNEL
最大脉冲漏极电流 (IDM):3 A认证状态:Not Qualified
表面贴装:YES端子面层:TIN LEAD
端子形式:GULL WING端子位置:SINGLE
处于峰值回流温度下的最长时间:NOT SPECIFIED晶体管应用:SWITCHING
晶体管元件材料:SILICONBase Number Matches:1

VP5225K4 数据手册

 浏览型号VP5225K4的Datasheet PDF文件第2页浏览型号VP5225K4的Datasheet PDF文件第3页 
VP5225  
P-Channel Enhancement-Mode  
Vertical DMOS FET  
Features  
General Description  
Low threshold (-2.4V max.)  
High input impedance  
Low input capacitance  
Fast switching speeds  
This low threshold, enhancement-mode (normally-off)  
transistor utilizes a vertical DMOS structSupertex’s  
well-proven, silicon-gate manufactcess. This  
combination produces a device wower andling  
capabilities of bipolar transistorthe high input  
impedance and positivteperature cient inherent  
in MOS devices. Chatic of all MOS structures, this  
device is free from theway d thermally-induced  
secondary breakdown.  
Low on-resistance  
Free from secondary breakdown  
Low input and output leakage  
Applications  
Medical Ultrasound imaging  
Non-destructive evaluation  
Solid state relays  
Supertex’s MOS FETs are ideally suited to a  
wide rangching nd amplifying applications where  
low td vtage, high breakdown voltage, high  
ipedaw input capacitance, and fast switching  
spedesired.  
Telecom switches  
Logic level interfaces – ideal for TTL and CMOS  
Ordering Information  
RDS(ON)  
(max)  
(Ω)  
ID(ON)  
(min)  
(A)  
Package Option  
DGS  
Device  
)  
3-Lead TO-252 (D-PA)  
VP5225  
VP5225K4  
-250  
3.0  
-2.5  
Pin Configuration  
Absolute Maximum s  
Parameter  
Value  
DRAIN  
Drain-to-sourcltage  
Drain-to-g
BVDSS  
BVDGS  
±20V  
SOURCE  
Gate-t
GATE  
Operamperature -55OC to +150OC  
Soldering *  
300OC  
3-Lead TO-252 (D-PAK) (K4)  
Product Marking  
Absolute Maximungs are those values beyond which damage to  
the device may occur. Functional operation under these conditions is  
not implied. Continuous operation of the device at the absolute rating  
level may affect device reliability. All voltages are referenced to device  
ground.  
YYWW  
VP5225  
LLLLLLL  
YY = Year Sealed  
WW = Week Sealed  
L = Lot Number  
* Distance of 1.6mm from case for 10 seconds.  
3-Lead TO-252 (D-PAK) (K4)  

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