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V62/06632-01XE PDF预览

V62/06632-01XE

更新时间： 2024-11-21 12:47:19
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
13页 531K
描述
DUAL INVERTER GATE

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V62/06632-01XE 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SOIC
包装说明：TSSOP, TSSOP6,.08针数：6
Reach Compliance Code：compliantHTS代码：8542.39.00.01
Factory Lead Time：8 weeks风险等级：5.74
系列：LVC/LCX/ZJESD-30 代码：R-PDSO-G6
JESD-609代码：e4长度：2 mm
负载电容（CL）：50 pF逻辑集成电路类型：INVERTER
最大I（ol）：0.032 A湿度敏感等级：1
功能数量：2输入次数：1
端子数量：6最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP6,.08
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法：TR峰值回流温度（摄氏度）：260
电源：3.3 V最大电源电流（ICC）：0.01 mA
Prop。Delay @ Nom-Sup：5 ns传播延迟（tpd）：8 ns
认证状态：Not Qualified施密特触发器：NO
座面最大高度：1.1 mm子类别：Gates
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：1.65 V
标称供电电压 (Vsup)：1.8 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：1.25 mm
Base Number Matches：1

V62/06632-01XE 数据手册

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SN74LVC2G04-EP  
DUAL INVERTER GATE  
www.ti.com  
SGLS365–AUGUST 2006  
FEATURES  
•
Controlled Baseline  
– One Assembly Site  
– One Test Site  
•
•
•
Ioff Supports Partial Power-Down-Mode  
Operation  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
– One Fabrication Site  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
•
•
Extended Temperature Performance of –55°C  
to 125°C  
Enhanced Diminishing Manufacturing  
Sources (DMS) Support  
– 1000-V Charged-Device Model (C101)  
(1)  
•
•
•
Enhanced Product-Change Notification  
Qualification Pedigree(1)  
Component qualification in accordance with JEDEC and  
industry standards to ensure reliable operation over an  
extended temperature range. This includes, but is not limited  
to, Highly Accelerated Stress Test (HAST) or biased 85/85,  
temperature cycle, autoclave or unbiased HAST,  
electromigration, bond intermetallic life, and mold compound  
life. Such qualification testing should not be viewed as  
justifying use of this component beyond specified  
performance and environmental limits.  
Available in the Texas Instruments  
NanoStar™ and NanoFree™ Packages  
•
•
•
•
•
•
Supports 5-V VCC Operation  
Inputs Accept Voltages to 5.5 V  
Max tpd of 4.1 ns at 3.3 V  
Low Power Consumption, 10-µA Max ICC  
±24-mA Output Drive at 3.3 V  
Typical VOLP (Output Ground Bounce) <0.8 V  
at VCC = 3.3 V, TA = 25°C  
•
Typical VOHV (Output VOH Undershoot) >2 V at  
VCC = 3.3 V, TA = 25°C  
YEA, YEP, YZA,  
OR YZP PACKAGE  
(BOTTOM VIEW)  
DBV PACKAGE  
(TOP VIEW)  
DCK PACKAGE  
(TOP VIEW)  
DRL PACKAGE  
(TOP VIEW)  
3
4
2Y  
2A  
GND  
1A  
1
2
3
6
5
4
1A  
GND  
2A  
1Y  
1A  
GND  
2A  
1Y  
1
2
3
6
5
4
1
2
3
6
1A  
GND  
2A  
1Y  
V
2
1
5
6
V
CC  
V
CC  
V
CC  
1Y  
2Y  
5
4
CC  
2Y  
2Y  
See mechanical drawings for dimensions.  
DESCRIPTION/ORDERING INFORMATION  
This dual inverter is designed for 1.65-V to 5.5-V VCC operation. The SN74LVC2G04 performs the Boolean  
function Y = A.  
NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the  
die as the package.  
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,  
preventing damaging current backflow through the device when it is powered down.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoStar, NanoFree are trademarks of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2006, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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