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V62/03666-01YE

更新时间： 2024-11-30 02:58:43
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
14页 500K
描述
TRIPLE 2-CHANNEL ANALOG MULTIPLEXER/DEMULTIP LEXER

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V62/03666-01YE 数据手册

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SCLS503C − MAY 2003 − REVISED MAY 2004  
D
Controlled Baseline  
− One Assembly/Test Site, One Fabrication  
Site  
D
Low Crosstalk Between Switches  
Individual Switch Controls  
D
D
D
Extremely Low Input Current  
D
D
D
D
D
D
Extended Temperature Performance of  
−40°C to 105°C  
Enhanced Diminishing Manufacturing  
Sources (DMS) Support  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
D
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
Enhanced Product-Change Notification  
†
Qualification Pedigree  
− 1000-V Charged-Device Model (C101)  
2-V to 5.5-V V  
Operation  
D OR PW PACKAGE  
(TOP VIEW)  
CC  
Supports Mixed-Mode Voltage Operation on  
All Ports  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
2Y1  
2Y0  
3Y1  
V
CC  
D
High On-Off Output-Voltage Ratio  
2-COM  
1-COM  
1Y1  
1Y0  
A
†
Component qualification in accordance with JEDEC and industry  
standards to ensure reliable operation over an extended  
temperature range. This includes, but is not limited to, Highly  
Accelerated Stress Test (HAST) or biased 85/85, temperature  
cycle, autoclave or unbiased HAST, electromigration, bond  
intermetallic life, and mold compound life. Such qualification  
testing should not be viewed as justifying use of this component  
beyond specified performance and environmental limits.  
3-COM  
3Y0  
INH  
GND  
GND  
B
C
description/ordering information  
This triple 2-channel CMOS analog multiplexer/demultiplexer is designed for 2-V to 5.5-V V  
operation.  
CC  
The SN74LV4053A handles both analog and digital signals. Each channel permits signals with amplitudes up  
to 5.5 V (peak) to be transmitted in either direction.  
Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for  
analog-to-digital and digital-to-analog conversion systems.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
‡
PACKAGE  
T
A
SOIC − D  
Tape and reel  
SN74LV4053ATDREP  
SN74LV4053ATPWREP  
LV4053ATEP  
L4053EP  
−40°C to 105°C  
TSSOP − PW Tape and reel  
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design  
guidelines are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
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Copyright 2004, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...14

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