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ꢎ ꢏꢐ ꢑꢒ ꢓꢔꢕ ꢉꢋ ꢐꢓ ꢔꢒ ꢖꢓ ꢕꢓ ꢒꢑꢏ ꢀꢓ ꢕ ꢔꢑꢏ ꢋꢗ ꢐ ꢅꢊ ꢀ ꢀꢐ ꢗ
SGUS042A − MAY 1998 − REVISED APRIL 2004
D
Controlled Baseline
− One Assembly/Test Site, One Fabrication
Site
D
1M-Bit On-Chip SRAM
− 512K-Bit Internal Program/Cache
(16K 32-Bit Instructions)
− 512K-Bit Dual-Access Internal Data
(64K Bytes)
D
D
D
D
D
Extended Temperature Performance up to
−40°C to 105°C
Enhanced Diminishing Manufacturing
Sources (DMS) Support
D
32-Bit External Memory Interface (EMIF)
− Glueless Interface to Synchronous
Memories: SDRAM and SBSRAM
− Glueless Interface to Asynchronous
Memories: SRAM and EPROM
− 52M-Byte Addressable External Memory
Space
Enhanced Product-Change Notification
†
Qualification Pedigree
Highest Performance Floating-Point Digital
Signal Processor (DSP) 320C6701
− 8.3-, 6-ns Instruction Cycle Time
− 120-, 167-MHz Clock Rate
− Eight 32-Bit Instructions/Cycle
− 1 GFLOPS
D
Four-Channel Bootloading
Direct-Memory-Access (DMA) Controller
With an Auxiliary Channel
D
D
16-Bit Host-Port Interface (HPI)
− Access to Entire Memory Map
− 320C6201 Fixed-Point DSP
Pin-Compatible
Two Multichannel Buffered Serial Ports
(McBSPs)
− Direct Interface to T1/E1, MVIP, SCSA
Framers
− ST-Bus-Switching Compatible
− Up to 256 Channels Each
− AC97-Compatible
− Serial-Peripheral-Interface (SPI)
Compatible (Motorola)
D
D
VelociTI Advanced Very Long Instruction
Word (VLIW) C67x CPU Core
− Eight Highly Independent Functional
Units:
− Four ALUs (Floating- and Fixed-Point)
− Two ALUs (Fixed-Point)
− Two Multipliers (Floating- and
Fixed-Point)
− Load-Store Architecture With 32 32-Bit
General-Purpose Registers
− Instruction Packing Reduces Code Size
− All Instructions Conditional
D
D
D
D
D
Two 32-Bit General-Purpose Timers
Flexible Phase-Locked-Loop (PLL) Clock
Generator
‡
Instruction Set Features
− Hardware Support for IEEE
Single-Precision Instructions
− Hardware Support for IEEE
Double-Precision Instructions
− Byte-Addressable (8-, 16-, 32-Bit Data)
− 8-Bit Overflow Protection
− Saturation
IEEE-1149.1 (JTAG )
Boundary-Scan-Compatible
352-Pin Ball Grid Array (BGA) Package
(GJC Suffix)
352-Pin Ball Grid Array (BGA) Mechanical
Shock-Tolerant Package (Mech~Shock)
Option (GJC Suffix)
D
0.18-µm/5-Level Metal Process
− CMOS Technology
− Bit-Field Extract, Set, Clear
− Bit-Counting
− Normalization
D
3.3-V I/Os, 1.8-V Internal (120-MHz)
3.3-V I/Os, 1.9-V Internal (167-MHz)
D
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
VelociTI is a trademark of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
†
Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range.
This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this
component beyond specified performance and environmental limits.
‡
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
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Copyright 2003, Texas Instruments Incorporated
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1
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