UTRON
UT62256C
32K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.0
FEATURES
GENERAL DESCRIPTION
ꢀ Access time : 35/70ns (max.)
ꢀ Low power consumption:
Operating : 40/30 mA (typical.)
Standby : 3mA (typical) normal
2uA (typical) L-version
The UT62256C is a 262,144-bit low power
CMOS static random access memory
organized as 32,768 words by 8 bits. It is
fabricated using high performance, high
reliability CMOS technology.
1uA (typical) LL-version
ꢀ Single 5V power supply
The UT62256C is designed for high-speed
ꢀ All inputs and outputs are TTL compatible
ꢀ Fully static operation
and low power application. It is particularly
well suited for battery back-up nonvolatile
memory application.
ꢀ Three state outputs
ꢀ Data retention voltage : 2V (min.)
ꢀ Package : 28-pin 600 mil PDIP
28-pin 330 mil SOP
The UT62256C operates from a single 5V
power supply and all inputs and outputs are
fully TTL compatible
28-pin 8mmx13.4mm STSOP
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
A4
A3
Vcc
WE
A14
A12
A7
1
28
27
2
3
26
25
A13
A8
A14
4
A6
.
.
.
V
CC
A13
A12
A7
A5
5
6
24
23
A9
MEMORY ARRAY
ROW
A4
A11
512 ROWS × 512 COLUMNS
DECODER
7
8
9
22
21
A3
V
SS
OE
A2
A10
A6
20
19
A1
CE
A5
A8
A0
10
11
I/O8
I/O7
I/O6
I/O5
I/O4
18
17
I/O1
I/O2
I/O3
Vss
12
. . .
13
14
16
15
I/O1
.
.
.
I/O
CONTROL
COLUMN I/O
.
.
.
.
.
.
I/O8
COLUMN DECODER
PDIP/SOP
CE
WE
OE
LOGIC
CONTROL
A10
CE
1
28
OE
A11
27
26
25
2
3
A10
A11
A9
A2 A1 A0
A9
A8
I/O8
I/O7
4
PIN DESCRIPTION
A13
WE
Vcc
5
6
24
23
I/O6
I/O5
I/O4
7
8
9
22
21
SYMBOL
DESCRIPTION
A14
A12
A7
Vss
I/O3
I/O2
I/O1
A0
UT62256C
A0 - A14
Address Inputs
20
19
I/O1 - I/O8
Data Inputs/Outputs
10
11
18
17
16
15
A6
Chip Enable Input
Write Enable Input
Output Enable Input
CE
WE
OE
VCC
VSS
12
13
14
A5
A4
A1
A3
A2
Power Supply
Ground
STSOP
____________________________________________________________________________________________
UTRON TECHNOLOGY INC.
P80027
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
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