Datasheet > UT61L512

UT61L512

更新时间： 2024-11-19 23:41:07

品牌	Logo	应用领域
其他 - ETC		/
页数	文件大小	规格书
10页	97K
描述
ASYNCHRONOUS STATIC RAM- High Speed

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数据手册

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UT61L512 数据手册



UTRON

UT61L512

64K X 8 BIT HIGH SPEED CMOS SRAM

Rev 1.2

FEATURES

GENERAL DESCRIPTION

Fast access time : 10/12/15 ns (max.)

Low operating power consumption :

60 mA (typical)

Single 3.3V power supply

All inputs and outputs TTL compatible

Fully static operation

Three state outputs

Package : 32-pin 300 mil SOJ

32-pin 8mmx20mm TSOP-I

The UT61L512 is a 524,288-bit high-speed

CMOS static random access memory organized

as 524,288 words by 8 bits. It is fabricated using

high performance, high reliability CMOS

technology.

The UT61L512 is designed for high-speed

system applications. It is particularly suited for

use in high-density high-speed system

applications.

The UT61L512 operates from a single 3.3V

power supply and all inputs and outputs are fully

TTL compatible.

FUNCTIONAL BLOCK DIAGRAM

A15

A13

PIN CONFIGURATION

A14

ROW

A12

MEMORY ARRAY

512 ROWS X 1024 COLUMNS

DECODER

Vcc

A15

CE2

A14

A12

A13

I/O1

I/O

CONTROL

A11

COLUMN I/O

I/O8

COLUMN DECODER

A10

CE1

I/O8

I/O7

CE1

LOGIC

CE2

CONTROL

I/O1

I/O2

I/O3

Vss

A10 A11

A3 A2 A1 A0

I/O6

I/O5

I/O4

PIN DESCRIPTION

SOJ

SYMBOL

A0 - A15

I/O1 - I/O8

DESCRIPTION

Address Inputs

Data Inputs/Outputs

Chip Enable 1, 2 Inputs

A11

A10

,CE2

CE1

A13

I/O8

I/O7

I/O6

I/O5

I/O4

Vss

I/O3

I/O2

I/O1

Write Enable Input

Output Enable Input

CE2

A15

V_CC

V_SS

Vcc

UT61L512

Power Supply

Ground

No Connection

A14

A12

TSOP-1

UTRON TECHNOLOGY INC.

P80024

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.

TEL: 886-3-5777882 FAX: 886-3-5777919

12 3 4 5 6 7...10

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