UTRON
UT61L512
64K X 8 BIT HIGH SPEED CMOS SRAM
Rev 1.2
FEATURES
GENERAL DESCRIPTION
Fast access time : 10/12/15 ns (max.)
Low operating power consumption :
60 mA (typical)
Single 3.3V power supply
All inputs and outputs TTL compatible
Fully static operation
Three state outputs
Package : 32-pin 300 mil SOJ
32-pin 8mmx20mm TSOP-I
The UT61L512 is a 524,288-bit high-speed
CMOS static random access memory organized
as 524,288 words by 8 bits. It is fabricated using
high performance, high reliability CMOS
technology.
The UT61L512 is designed for high-speed
system applications. It is particularly suited for
use in high-density high-speed system
applications.
The UT61L512 operates from a single 3.3V
power supply and all inputs and outputs are fully
TTL compatible.
FUNCTIONAL BLOCK DIAGRAM
A15
A13
PIN CONFIGURATION
.
A14
ROW
V
CC
A12
A7
MEMORY ARRAY
512 ROWS X 1024 COLUMNS
DECODER
NC
NC
Vcc
A15
1
2
32
.
.
31
30
29
V
SS
A6
CE2
A14
A12
3
A5
A4
A8
4
WE
A13
A8
5
28
27
26
25
24
23
22
21
20
19
18
17
A7
A6
6
.
.
.
A5
A4
A9
7
I/O1
.
I/O
CONTROL
A11
8
.
COLUMN I/O
.
.
.
.
.
.
A3
9
OE
.
I/O8
COLUMN DECODER
A2
A10
10
11
A1
CE1
I/O8
I/O7
CE1
LOGIC
A0
12
13
14
15
16
CE2
CONTROL
I/O1
I/O2
I/O3
Vss
A9
A10 A11
A3 A2 A1 A0
WE
OE
I/O6
I/O5
I/O4
PIN DESCRIPTION
SOJ
SYMBOL
A0 - A15
I/O1 - I/O8
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip Enable 1, 2 Inputs
A11
A9
1
2
3
4
5
6
7
8
9
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A10
A8
,CE2
CE1
A13
I/O8
I/O7
I/O6
I/O5
I/O4
Vss
I/O3
I/O2
I/O1
A0
Write Enable Input
Output Enable Input
WE
CE2
A15
OE
VCC
VSS
NC
Vcc
NC
NC
UT61L512
Power Supply
Ground
No Connection
10
11
12
13
14
15
16
A14
A12
A7
A6
A1
A2
A3
A5
A4
TSOP-1
UTRON TECHNOLOGY INC.
P80024
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
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