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USB3500-ABZJTR PDF预览

USB3500-ABZJTR

更新时间: 2024-11-25 20:07:07
品牌 Logo 应用领域
美国微芯 - MICROCHIP 通信时钟外围集成电路
页数 文件大小 规格书
45页 731K
描述
SERIAL COMM CONTROLLER

USB3500-ABZJTR 技术参数

生命周期:Active包装说明:HVQCCN,
Reach Compliance Code:compliant风险等级:5.75
地址总线宽度:边界扫描:NO
最大时钟频率:24 MHz通信协议:SYNC; BIT
数据编码/解码方法:NRZI外部数据总线宽度:8
JESD-30 代码:S-XQCC-N56长度:8 mm
低功率模式:YES串行 I/O 数:1
端子数量:56最高工作温度:85 °C
最低工作温度:封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE筛选级别:TS 16949
座面最大高度:1 mm最大供电电压:3.6 V
最小供电电压:3 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:OTHER端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
宽度:8 mmuPs/uCs/外围集成电路类型:SERIAL IO/COMMUNICATION CONTROLLER, SERIAL
Base Number Matches:1

USB3500-ABZJTR 数据手册

 浏览型号USB3500-ABZJTR的Datasheet PDF文件第2页浏览型号USB3500-ABZJTR的Datasheet PDF文件第3页浏览型号USB3500-ABZJTR的Datasheet PDF文件第4页浏览型号USB3500-ABZJTR的Datasheet PDF文件第5页浏览型号USB3500-ABZJTR的Datasheet PDF文件第6页浏览型号USB3500-ABZJTR的Datasheet PDF文件第7页 
USB3500  
Hi-Speed USB Host, Device or OTG PHY  
With UTMI+ Interface  
• Integrated 24MHz Crystal Oscillator supports  
either crystal operation or 24MHz external clock  
input  
Highlights  
• USB-IF “Hi-Speed” certified to the Universal Serial  
Bus Specification Rev 2.0  
• Internal PLL for 480MHz Hi-Speed USB operation  
• Supports USB 2.0 and legacy USB 1.1 devices  
• Interface compliant with the UTMI+ Specification,  
Revision 1.0  
• 55mA Unconfigured Current (typical) - ideal for  
bus powered applications  
• Includes full support for the optional On-The-Go  
(OTG) protocol detailed in the On-The-Go Sup-  
plement Revision 1.0a specification  
• 83uA suspend current (typical) - ideal for battery  
powered applications  
• Functional as a host, device or OTG PHY  
• Supports HS, FS, and LS data rates  
• Full Commercial operating temperature range  
from 0C to +70C  
• Supports FS pre-amble for FS hubs with a LS  
device attached (UTMI+ Level 3)  
• 56-Pin, QFN RoHS compliant package  
(8 x 8 x 0.90 mm height)  
• Supports HS SOF and LS keep alive pulse.  
• Supports Host Negotiation Protocol (HNP) and  
Session Request protocol (SRP)  
Functional Overview  
The USB3500 is a highly integrated USB transceiver  
system. It contains a complete USB 2.0 PHY with the  
UTMI+ industry standard interface to support fast time  
to market for a USB controller. The USB3500 is com-  
posed of the functional blocks shown in the figure  
below.  
• Internal comparators support OTG monitoring of  
VBUS levels  
• Low Latency Hi-Speed Receiver (43 Hi-Speed  
clocks Max)  
• Internal 1.8 volt regulators allow operation from a  
single 3.3 volt supply  
• Internal short circuit protection of ID, DP and DM  
lines to VBUS or ground  
USB3500 Block Diagram  
5V  
24 MHz  
XTAL  
Power  
Supply  
Internal  
Regulators  
& POR  
VBUS  
ID  
OTG  
Module  
XTAL &  
PLL  
VDD3.3  
VDD3.3  
XCVRSEL[1:0]  
TERMSEL  
Mini-AB  
USB  
Connector  
TXREADY  
SUSPENDN  
TXVALID  
RESET  
CHRGVBUS  
RXACTIVE  
TX  
Logic  
DP  
DM  
OPMODE[1:0]  
HS XCVR  
ID_DIG  
IDPULLUP  
CLKOUT  
LINESTATE[1:0]  
HOSTDISC  
DISCHRGVBUS  
SESSEND  
DATA[7:0]  
RXVALID  
SESSVLD  
DPPD  
DMPD  
Resistors  
RX  
Logic  
Bias  
Gen.  
RBIAS  
FS/LS  
XCVR  
UTMI+  
Digital  
RXERROR  
VBUSVLD  
USB3500  
2005 - 2016 Microchip Technology Inc.  
DS00002103A-page 1  

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