5秒后页面跳转
UR5596G-S08-R PDF预览

UR5596G-S08-R

更新时间: 2024-11-27 01:23:23
品牌 Logo 应用领域
友顺 - UTC 双倍数据速率接口集成电路
页数 文件大小 规格书
11页 260K
描述
DDR TERMINATION REGULATOR

UR5596G-S08-R 技术参数

生命周期:Active包装说明:,
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.59
接口集成电路类型:BUS TERMINATOR SUPPORT CIRCUITBase Number Matches:1

UR5596G-S08-R 数据手册

 浏览型号UR5596G-S08-R的Datasheet PDF文件第2页浏览型号UR5596G-S08-R的Datasheet PDF文件第3页浏览型号UR5596G-S08-R的Datasheet PDF文件第4页浏览型号UR5596G-S08-R的Datasheet PDF文件第5页浏览型号UR5596G-S08-R的Datasheet PDF文件第6页浏览型号UR5596G-S08-R的Datasheet PDF文件第7页 
UNISONIC TECHNOLOGIES CO., LTD  
UR5596  
CMOS IC  
DDR TERMINATION  
REGULATOR  
DESCRIPTION  
The UTC UR5596 is a linear bus termination regulator and  
designed to meet JEDEC SSTL-2(Stub-Series Terminated Logic)  
specifications for termination of DDR-SDRAM. It also can be  
used in SSTL-3 or HSTL (High-Speed Transceiver Logic)  
scheme. The device contains a high-speed OP AMP to provide  
excellent response to the load transients, and can deliver 1.5A  
continuous current and transient peaks up to 3A in the application  
as required for DDR-SDRAM termination.  
The UTC UR5596 also incorporates a VSENSE pin to provide  
superior load regulation and a VREF output as a reference for the  
chipset and DIMMs. Besides, an active low shutdown (SHDN) pin  
provides Suspend To RAM (STR) functionality. When SHDN is  
pulled low the VTT output will tri-state providing a high impedance  
output, but, VREF will remain active. A power savings advantage  
can be obtained in this mode through lower quiescent current.  
Regarding the output, VTT is capable of sinking and sourcing  
current while regulating the output voltage equal to VDDQ/2. The  
output stage has been designed to maintain excellent load  
regulation while preventing shoot through. The UTC UR5596 also  
incorporates two distinct power rails that separates the analog  
circuitry from the power output stage. This allows a split rail  
approach to be utilized to decrease internal power dissipation and  
permits UTC UR5596 to provide a termination solution for DDRII  
SDRAM.  
FEATURES  
* Source and sink current  
* Low output voltage offset  
* No external resistors required  
* Linear topology  
* Suspend To Ram (STR) functionality  
* Low external component count  
* Thermal shutdown protection  
ORDERING INFORMATION  
Ordering Number  
UR5596G-S08-R  
UR5596G-SH2-R  
Package  
SOP-8  
Packing  
Tape Reel  
Tape Reel  
HSOP-8  
www.unisonic.com.tw  
1 of 11  
Copyright © 2014 Unisonic Technologies Co., Ltd  
QW-R502-045.D  

与UR5596G-S08-R相关器件

型号 品牌 获取价格 描述 数据表
UR5596G-SH2-R UTC

获取价格

Terminator Support Circuit
UR5596L-S08-R UTC

获取价格

MOS IC
UR5596L-S08-T UTC

获取价格

MOS IC
UR5596L-SH2-R UTC

获取价格

DDR TERMINATION REGULATOR
UR5596L-SH2-T UTC

获取价格

DDR TERMINATION REGULATOR
UR5596-S08-R UTC

获取价格

MOS IC
UR5596-S08-T UTC

获取价格

MOS IC
UR5596-SH2-R UTC

获取价格

DDR TERMINATION REGULATOR
UR5596-SH2-T UTC

获取价格

DDR TERMINATION REGULATOR
UR5597RP500G ETC

获取价格

LV POLYURETHANE 500G