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UR5596-SH2-R

更新时间： 2024-11-26 05:55:11

品牌	Logo	应用领域
友顺 - UTC		稳压器双倍数据速率
页数	文件大小	规格书
12页	219K
描述
DDR TERMINATION REGULATOR

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技术参数
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UR5596-SH2-R 技术参数

生命周期：	Active	零件包装代码：	SOIC
包装说明：	HSOP,	针数：	8
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.59
接口集成电路类型：	BUS TERMINATOR SUPPORT CIRCUIT	JESD-30 代码：	R-PDSO-G8
JESD-609代码：	e0	长度：	4.92 mm
功能数量：	1	端子数量：	8
最高工作温度：	125 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	HSOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, HEAT SINK/SLUG
认证状态：	Not Qualified	座面最大高度：	1.96 mm
标称供电电压：	2.5 V	表面贴装：	YES
技术：	CMOS	温度等级：	OTHER
端子面层：	TIN LEAD	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
宽度：	3.95 mm	Base Number Matches：	1

UR5596-SH2-R 数据手册

UNISONIC TECHNOLOGIES CO., LTD

UR5596

CMOS IC

DDR TERMINATION

REGULATOR

DESCRIPTION

The UTC UR5596 is a linear bus termination regulator and

designed to meet JEDEC SSTL-2(Stub-Series Terminated Logic)

specifications for termination of DDR-SDRAM. It also can be

used in SSTL-3 or HSTL (High-Speed Transceiver Logic)

scheme. The device contains a high-speed OP AMP to provide

excellent response to the load transients, and can deliver 1.5A

continuous current and transient peaks up to 3A in the application

as required for DDR-SDRAM termination.

The UTC UR5596 also incorporates a V_SENSEpin to provide

superior load regulation and a V_REFoutput as a reference for the

chipset and DIMMs. Besides, an active low shutdown (SHDN) pin

provides Suspend To RAM (STR) functionality. When SHDN is

pulled low the V_TToutput will tri-state providing a high impedance

output, but, V_REFwill remain active. A power savings advantage

can be obtained in this mode through lower quiescent current.

Regarding the output, V_TTis capable of sinking and sourcing

current while regulating the output voltage equal to V_DDQ/2. The

output stage has been designed to maintain excellent load

regulation while preventing shoot through. The UTC UR5596 also

incorporates two distinct power rails that separates the analog

circuitry from the power output stage. This allows a split rail

approach to be utilized to decrease internal power dissipation and

permits UTC UR5596 to provide a termination solution for DDRII

SDRAM.

*Pb-free plating product number: UR5596L

FEATURES

* Source and sink current

* Low output voltage offset

* No external resistors required

* Linear topology

* Suspend To Ram (STR) functionality

* Low external component count

* Thermal shutdown protection

ORDERING INFORMATION

Ordering Number

Package

Packing

Normal

Lead Free Plating

UR5596-S08-R

UR5596-S08-T

UR5596-SH2-R

UR5596-SH2-T

UR5596L-S08-R

UR5596L-S08-T

UR5596L-SH2-R

UR5596L-SH2-T

SOP-8

Tape Reel

Tube

HSOP-8

Tape Reel

Tube

UR5596L-S08-R

(1) Packing Type

(2) Package Type

(3) Lead Plating

(1) R: Tape Reel, T: Tube

(2) S08: SOP-8

(3) L: Lead Free Plating, Blank: Pb/Sn

www.unisonic.com.tw

1 of 12

QW-R502-045,C

12 3 4 5 6 7...12

中文翻译

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