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UPSD3313D-24U6 PDF预览

UPSD3313D-24U6

更新时间: 2024-11-07 06:01:39
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意法半导体 - STMICROELECTRONICS /
页数 文件大小 规格书
123页 1145K
描述
IC,MICROCONTROLLER,8-BIT,8051 CPU,CMOS,QFP,80PIN,PLASTIC

UPSD3313D-24U6 数据手册

 浏览型号UPSD3313D-24U6的Datasheet PDF文件第2页浏览型号UPSD3313D-24U6的Datasheet PDF文件第3页浏览型号UPSD3313D-24U6的Datasheet PDF文件第4页浏览型号UPSD3313D-24U6的Datasheet PDF文件第5页浏览型号UPSD3313D-24U6的Datasheet PDF文件第6页浏览型号UPSD3313D-24U6的Datasheet PDF文件第7页 
µPSD33XX (TURBO SERIES)  
Fast 8032 MCU With Programmable Logic  
PRELIMINARY DATA  
FEATURES SUMMARY  
8-bit System On Chip for Embedded Control  
Programmable Counter Array (PCA)  
– Dual independent timer/counter blocks, each  
with three 16-bit timer/counters modules  
– Use any of the 6 modules as: 16-bit capture/  
compare, 16-bit timer/counter, 8/16 bit PWM.  
The Turbo µPSD3300 Series combines a power-  
ful, 8051-based microcontroller with a unique  
memory structure, programmable logic, and a rich  
peripheral mix to form the ideal SOC for embed-  
ded control. At it's core is a fast, 4-cycle 8032 MCU  
with a 6-byte instruction prefetch queue and a 4-  
entry, fully associative branching cache to maxi-  
mize MCU performance, enabling smaller loops of  
code to execute very quickly.  
JTAG Debug and In-System Programming  
– Set Breakpoints, trace, single-step, display,  
modify memory, and SFRs; external event  
pin.  
Code development is easily managed without a  
hardware In-Circuit Emulator by using the serial  
JTAG debug interface. JTAG is also used for In-  
System Programming (ISP), perfect for manufac-  
turing and lab development. The 8032 core is cou-  
pled to Programmable System Device (PSD)  
architecture to optimize 8032 memory structure,  
offering two independent banks of Flash memory  
that can be placed at virtually any address within  
8032 program or data space, and easily paged be-  
yond 64K bytes using on-chip programmable de-  
code logic. Dual Flash memory banks provide a  
robust solution for remote product updates in the  
field through In-Application Programming (IAP).  
Dual Flash banks also support EEPROM emula-  
tion, eliminating the need for external EEPROM  
chips.  
– ISP the chip in 10-20sec, 8032 not involved.  
Programmable Logic, General Purpose  
– 16 Macrocells with architecture similar to in-  
dustry standard 22V10 PLDs  
– Create shifters, state machines, chip-selects,  
glue-logic to keypads, panels, LCDs, others  
– Configure PLD with simple PSDsoft Express  
software ... download at no charge from web.  
Dual Flash Memories w/Memory Managment  
– True READ-while-WRITE concurrent access  
– Main Flash size: 64K, 128K, or 256K Bytes  
– Secondary Flash size: 16K or 32K bytes  
– 100,000 min erase cycles, 15 year retention  
– On-chip programmable memory decode logic  
SRAM  
A wide variety of Flash and SRAM memory sizes  
are available, some reaching the largest on the 8-  
bit MCU market today. General purpose program-  
mable logic is included to build an endless variety  
of glue-logic, saving external chips. This SOC also  
– 2K, 8K, or 32K Bytes; use as XDATA or code.  
– Capable of battery backup w/external battery.  
Peripheral Interfaces  
provides a rich array of peripherals, including ana-  
log and supervisor functions.  
Fast Turbo 8032 MCU  
– (8) 10-bit ADC channels, 8 usec conversion  
time  
2
– Advanced 8032 core: four clocks per instruc-  
tion instruction pre-fetch; branching cache  
– 10 MIPs peak performance @40MHz clock  
– I C Master/Slave bus controller up to 800kHz  
– SPI Master bus controller, up to 10Mhz  
– Two standard UARTs with independent baud  
– IrDA protocol support up to 115K baud rate  
– 8032 address/data bus (80 pin package only)  
– Up to 46 I/O; eight can sink/source 10mA.  
Supervisor Functions  
5.0V V ... 8 MIPs peak @40MHz, 3.3V V  
CC  
CC  
– 8032 core compatible with 3rd party tools  
– Internal clock divider for low-power mode  
– Three 8032 16-bit timers and external  
interrupts  
– Watchdog timer, V monitor with 10ms  
CC  
– Dual XDATA pointers with auto incr & decr  
Reset generator, Filtered Reset input  
July 2003  
1/123  
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.  
Rev. 1.0  

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