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UPD720102F1-CA7-A PDF预览

UPD720102F1-CA7-A

更新时间： 2024-11-06 20:11:11
品牌 Logo 应用领域
日电电子 - NEC /
页数 文件大小 规格书
36页 327K
描述
USB Bus Controller, CMOS, PBGA121, 8 X 8 MM, LEAD FREE, PLASTIC, FBGA-121

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中文翻译

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UPD720102F1-CA7-A 技术参数

是否Rohs认证： 符合生命周期：Transferred
包装说明：8 X 8 MM, LEAD FREE, PLASTIC, FBGA-121Reach Compliance Code：compliant
风险等级：5.71地址总线宽度：32
最大时钟频率：48 MHz外部数据总线宽度：32
JESD-30 代码：S-PBGA-B121JESD-609代码：e1
长度：8 mm端子数量：121
最高工作温度：70 °C最低工作温度：-20 °C
封装主体材料：PLASTIC/EPOXY封装代码：TFBGA
封装形状：SQUARE封装形式：GRID ARRAY, THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）：260认证状态：Not Qualified
座面最大高度：1.09 mm最大供电电压：3.465 V
最小供电电压：3.135 V标称供电电压：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：TIN SILVER COPPER
端子形式：BALL端子节距：0.65 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：10
宽度：8 mmuPs/uCs/外围集成电路类型：BUS CONTROLLER, UNIVERSAL SERIAL BUS
Base Number Matches：1

UPD720102F1-CA7-A 数据手册

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DATA SHEET  
MOS INTEGRATED CIRCUIT  
μPD720102  
USB 2.0 HOST CONTROLLER  
The μPD720102 complies with the universal serial bus specification revision 2.0 and open host controller interface  
specification for full-/low-speed signaling and Intel's enhanced host controller interface specification for high-speed  
signaling and works up to 480 Mbps. The μPD720102 is integrated 2 host controller cores with PCI interface and USB  
2.0 transceivers into a single chip.  
Detailed function descriptions are provided in the following user’s manual. Be sure to read the manual before designing.  
μPD720102 User’s Manual: S17999E  
FEATURES  
•
•
•
•
Compliant with universal serial bus specification revision 2.0 (data rate: 1.5/12/480 Mbps)  
Compliant with open host controller interface specification for USB release 1.0a  
Compliant with enhanced host controller interface specification for USB revision 1.0  
PCI multi-function device consists of one OHCI host controller core for full-/low-speed signaling and one EHCI host  
controller core for high-speed signaling  
•
•
Root hub with 3 (Max.) downstream facing ports which are shared by OHCI and EHCI host controller cores  
All downstream facing ports can handle high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps)  
transaction  
•
•
•
•
•
•
•
•
•
•
Supports hyper-speed transfer mode using HSMODE signal  
32-bit 33 MHz host interface compliant with PCI specification revision 2.2  
Supports PCI mobile design guide version 1.1  
Supports PCI-bus power management interface specification revision 1.1  
PCI bus bus-master access  
Supports 3.3 V PCI  
System clock is generated by 30 MHz crystal or 48 MHz clock input  
Operational registers direct-mapped to PCI memory space  
3.3 V single power supply, 1.5 V internal operating voltage from on chip regulator  
On chip Rs and Rpd resistors for USB signals  
ORDERING INFORMATION  
Part Number  
Package  
Remark  
μPD720102GC-YEB-A  
μPD720102F1-CA7-A  
120-pin plastic TQFP (fine pitch) (14 × 14)  
121-pin plastic FBGA (8 × 8)  
Lead-free product  
Lead-free product  
<R>  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all products and/or types are available in every country. Please check with an NEC Electronics  
sales representative for availability and additional information.  
Document No. S17998EJ4V0DS00 (4th edition)  
Date Published March 2007 NS CP (N)  
Printed in Japan  
The mark "<R>" shows major revised points.  
2006  
1234567...36

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