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UPD703032AGF-XXX-3BA PDF预览

UPD703032AGF-XXX-3BA

更新时间: 2024-10-30 15:56:11
品牌 Logo 应用领域
日电电子 - NEC 时钟微控制器外围集成电路
页数 文件大小 规格书
52页 441K
描述
Microcontroller, 32-Bit, MROM, 20MHz, MOS, PQFP100, 14 X 20 MM, PLASTIC, QFP-100

UPD703032AGF-XXX-3BA 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:QFP,
针数:100Reach Compliance Code:compliant
HTS代码:8542.31.00.01风险等级:5.51
具有ADC:YES地址总线宽度:22
位大小:32最大时钟频率:20 MHz
DAC 通道:NODMA 通道:YES
外部数据总线宽度:16JESD-30 代码:R-PQFP-G100
JESD-609代码:e0长度:20 mm
I/O 线路数量:83端子数量:100
最高工作温度:85 °C最低工作温度:-40 °C
PWM 通道:NO封装主体材料:PLASTIC/EPOXY
封装代码:QFP封装形状:RECTANGULAR
封装形式:FLATPACK峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not QualifiedROM可编程性:MROM
座面最大高度:3 mm速度:20 MHz
最大供电电压:5.5 V最小供电电压:4 V
标称供电电压:5 V表面贴装:YES
技术:MOS温度等级:INDUSTRIAL
端子面层:TIN LEAD端子形式:GULL WING
端子节距:0.65 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:14 mm
uPs/uCs/外围集成电路类型:MICROCONTROLLERBase Number Matches:1

UPD703032AGF-XXX-3BA 数据手册

 浏览型号UPD703032AGF-XXX-3BA的Datasheet PDF文件第2页浏览型号UPD703032AGF-XXX-3BA的Datasheet PDF文件第3页浏览型号UPD703032AGF-XXX-3BA的Datasheet PDF文件第4页浏览型号UPD703032AGF-XXX-3BA的Datasheet PDF文件第5页浏览型号UPD703032AGF-XXX-3BA的Datasheet PDF文件第6页浏览型号UPD703032AGF-XXX-3BA的Datasheet PDF文件第7页 
DATA SHEET  
MOS INTEGRATED CIRCUITS  
µPD703032A, 703032AY,  
70F3032A, 70F3032AY  
V850/SB1TM  
32-BIT SINGLE-CHIP MICROCONTROLLERS  
DESCRIPTION  
The µPD703032A, 703032AY, 70F3032A, and 70F3032AY (V850/SB1) are 32-bit single-chip microcontrollers of  
the V850 SeriesTM for AV equipment. 32-bit CPU, ROM, RAM, timer/counters, serial interfaces, A/D converter, DMA  
controller, and so on are integrated on a single chip.  
The µPD70F3032A and 70F3032AY have flash memory in place of the internal mask ROM of the µPD703032A  
and 703032AY. Because flash memory allows the program to be written and erased electrically with the device  
mounted on the board, these products are ideal for the evaluation stages of system development, small-scale  
production, and rapid development of new products.  
The µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY products with a different ROM/RAM  
size are also available.  
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before  
designing.  
V850/SB1, V850/SB2TM User’s Manual Hardware: U13850E  
V850 Series User’s Manual Architecture:  
U10243E  
FEATURES  
{ Number of instructions: 74  
{ Minimum instruction execution time: 50 ns (@ internal 20 MHz operation)  
{ General-purpose registers: 32 bits × 32 registers  
{ Instruction set: Signed multiplication, saturation operations, 32-bit shift instructions, bit manipulation instructions,  
load/store instructions  
{ Memory space: 16 MB linear address space  
{ Internal memory ROM: 512 KB (µPD703032A, 703032AY: mask ROM)  
512 KB (µPD70F3032A, 70F3032AY: flash memory)  
RAM: 24 KB (µPD703032A, 703032AY, 70F3032A, 70F3032AY)  
{ Interrupt/exception: µPD703032A, 70F3032A (external: 8, internal: 31 sources, exception: 1 source)  
µPD703032AY, 70F3032AY (external: 8, internal: 32 sources, exception: 1 source)  
{ I/O lines Total: 83  
{ Timer/counters: 16-bit timer (2 channels: TM0, TM1)  
8-bit timer (6 channels: TM2 to TM7)  
{ Watch timer: 1 channel  
{ Watchdog timer: 1 channel  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all devices/types available in every country. Please check with local NEC representative for  
availability and additional information.  
Document No. U14893EJ2V0DS00 (2nd edition)  
Date Published February 2002 J CP(K)  
Printed in Japan  
The mark  
shows major revised points.  
©
2000  

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