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UPD4481362GF-C50-A

更新时间： 2024-12-01 05:23:27
品牌 Logo 应用领域
日电电子 - NEC ISM频段静态存储器内存集成电路
页数 文件大小 规格书
40页 223K
描述
256KX36 ZBT SRAM, 3.2ns, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, LQFP-100

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UPD4481362GF-C50-A 技术参数

生命周期：Transferred零件包装代码：QFP
包装说明：LQFP,针数：100
Reach Compliance Code：unknownECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.56
最长访问时间：3.2 nsJESD-30 代码：R-PQFP-G100
JESD-609代码：e6长度：20 mm
内存密度：9437184 bit内存集成电路类型：ZBT SRAM
内存宽度：36功能数量：1
端子数量：100字数：262144 words
字数代码：256000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：256KX36封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装形状：RECTANGULAR
封装形式：FLATPACK, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：NOT SPECIFIED认证状态：Not Qualified
座面最大高度：1.7 mm最大供电电压 (Vsup)：2.625 V
最小供电电压 (Vsup)：2.375 V标称供电电压 (Vsup)：2.5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：TIN BISMUTH
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：14 mmBase Number Matches：1

UPD4481362GF-C50-A 数据手册

 浏览型号UPD4481362GF-C50-A的Datasheet PDF文件第2页浏览型号UPD4481362GF-C50-A的Datasheet PDF文件第3页浏览型号UPD4481362GF-C50-A的Datasheet PDF文件第4页浏览型号UPD4481362GF-C50-A的Datasheet PDF文件第5页浏览型号UPD4481362GF-C50-A的Datasheet PDF文件第6页浏览型号UPD4481362GF-C50-A的Datasheet PDF文件第7页 
PRELIMINARY DATA SHEET  
MOS INTEGRATED CIRCUIT  
µ
PD4481162, 4481182, 4481322, 4481362  
8M-BIT ZEROSBTM SRAM  
PIPELINED OPERATION  
Description  
The µPD4481162 is a 524,288-word by 16-bit, the µPD4481182 is a 524,288-word by 18-bit, the µPD4481322 is a  
262,144-word by 32-bit and the µPD4481362 is a 262,144-word by 36-bit ZEROSB static RAM fabricated with  
advanced CMOS technology using full CMOS six-transistor memory cell.  
The µPD4481162, µPD4481182, µPD4481322 and µPD4481362 are optimized to eliminate dead cycles for read to  
write, or write to read transitions. These ZEROSB static RAMs integrate unique synchronous peripheral circuitry, 2-bit  
burst counter and output buffer as well as SRAM core. All input registers are controlled by a positive edge of the  
single clock input (CLK).  
The µPD4481162, µPD4481182, µPD4481322 and µPD4481362 are suitable for applications which require  
synchronous operation, high speed, low voltage, high density and wide bit configuration, such as buffer memory.  
ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State (“Sleep”).  
In the “Sleep” state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes normal  
operation.  
The µPD4481162, µPD4481182, µPD4481322 and µPD4481362 are packaged in 100-pin PLASTIC LQFP with a 1.4  
mm package thickness or 165-pin TAPE FBGA for high density and low capacitive loading.  
Features  
• Low voltage core supply (A version : VDD = 3.3 ± 0.165V, C version : VDD = 2.5 ± 0.125V)  
• Synchronous operation  
• 100 percent bus utilization  
• Internally self-timed write control  
• Burst read / write : Interleaved burst and linear burst sequence  
• Fully registered inputs and outputs for pipelined operation  
• All registers triggered off positive clock edge  
• 3.3V or 2.5V LVTTL Compatible : All inputs and outputs  
• Fast clock access time : 3.2 ns (200 MHz), 3.5 ns (167 MHz) , 4.2 ns (133 MHz)  
• Asynchronous output enable : /G  
• Burst sequence selectable : MODE  
• Sleep mode : ZZ (ZZ = Open or Low : Normal operation)  
• Separate byte write enable : /BW1 - /BW4 (µPD4481322 and µPD4481362), /BW1 - /BW2 (µPD4481162 and µPD4481182)  
• Three chip enables for easy depth expansion  
• Common I/O using three state outputs  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all devices/types available in every country. Please check with local NEC representative for  
availability and additional information.  
Document No. M15562EJ1V0DS00 (1st edition)  
Date Published June 2001 NS CP(K)  
Printed in Japan  
2001  
©
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