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UPD44647184F5-E27-FQ1 PDF预览

UPD44647184F5-E27-FQ1

更新时间: 2023-01-15 00:00:00
品牌 Logo 应用领域
日电电子 - NEC 静态存储器
页数 文件大小 规格书
36页 479K
描述
QDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, PLASTIC, BGA-165

UPD44647184F5-E27-FQ1 数据手册

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PRELIMINARY DATA SHEET  
MOS INTEGRATED CIRCUIT  
μPD44647094,44647184,44647364,44647096,44647186,44647366  
72M-BIT QDRTM II+ SRAM  
2.0 & 2.5 Cycle Read Latency  
4-WORD BURST OPERATION  
Description  
The μPD44647094 and μPD44647096 are 8,388,608-word by 9-bit, the μPD44647184 and μPD44647186 are  
4,194,304-word by 18-bit and the μPD44647364 and μPD44647366 are 2,097,152-word by 36-bit synchronous quad data  
rate static RAMs fabricated with advanced CMOS technology using full CMOS six-transistor memory cell.  
The μPD44647xx4 is for 2.0 cycle and the μPD44647xx6 is for 2.5 cycle read latency. The μPD44647094,  
μPD44647096, μPD44647184, μPD44647186, μPD44647364 and μPD44647366 integrate unique synchronous  
peripheral circuitry and a burst counter. All input registers controlled by an input clock pair (K and K#) are latched on  
the positive edge of K and K#.  
These products are suitable for application which require synchronous operation, high speed, low voltage, high density  
and wide bit configuration.  
These products are packaged in 165-pin PLASTIC BGA.  
Features  
Core (VDD) = 1.8 ± 0.1 V power supply  
I/O (VDDQ) = 1.5 ± 0.1 V power supply  
165-pin PLASTIC BGA (15x17)  
HSTL interface  
PLL circuitry for wide output data valid window and future frequency scaling  
Separate independent read and write data ports with concurrent transactions  
100% bus utilization DDR READ and WRITE operation  
Four-tick burst for reduced address frequency  
Two input clocks (K and K#) for precise DDR timing at clock rising edges only  
Two Echo clocks (CQ and CQ#)  
Data Valid pin (QVLD) supported  
Read latency : 2.0 & 2.5 clock cycles (Not selectable by user)  
Internally self-timed write control  
Clock-stop capability. Normal operation is restored in 2,048 cycles after clock is resumed.  
User programmable impedance output (35 to 70 Ω)  
Fast clock cycle time : 2.66 ns (375 MHz) for 2.0 cycle read latency,  
2.5 ns (400 MHz) for 2.5 cycle read latency  
Simple control logic for easy depth expansion  
JTAG 1149.1 compatible test access port  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all products and/or types are available in every country. Please check with an NEC Electronics  
sales representative for availability and additional information.  
Document No. M18526EJ1V0DS00 (1st edition)  
Date Published November 2006 NS CP(N)  
Printed in Japan  
2006  

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