Datasheet > UPD4382161GF-A10

UPD4382161GF-A10

更新时间： 2024-11-05 23:40:15

品牌	Logo	应用领域
其他 - ETC		静态存储器
页数	文件大小	规格书
24页	195K
描述
x16 Fast Synchronous SRAM

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UPD4382161GF-A10 数据手册

DATA SHEET

MOS INTEGRATED CIRCUIT

PD4382161, 4382181, 4382321, 4382361

8M-BIT CMOS SYNCHRONOUS FAST SRAM

FLOW THROUGH OPERATION

Description

The µPD4382161 is a 524,288-word by 16-bit, the µPD4382181 is a 524,288-word by 18-bit, the µPD4382321 is a

262,144-word by 32-bit and the µPD4382361 is a 262,144-word by 36-bit synchronous static RAM fabricated with

advanced CMOS technology using N-channel four-transistor memory cell.

The µPD4382161, µPD4382181, µPD4382321 and µPD4382361 integrate unique synchronous peripheral circuitry, 2-bit

burst counter and output buffer as well as SRAM core. All input registers are controlled by a positive edge of the single

clock input (CLK).

The µPD4382161, µPD4382181, µPD4382321 and µPD4382361 are suitable for applications which require synchronous

operation, high speed, low voltage, high density and wide bit configuration, such as cache and buffer memory.

ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State (“Sleep”). In

the “Sleep” state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes normal operation.

The µPD4382161, µPD4382181, µPD4382321 and µPD4382361 are packaged in 100-pin plastic LQFP with a 1.4 mm

package thickness for high density and low capacitive loading.

Features

• Single 3.3 V power supply

• Synchronous operation

• Internally self-timed write control

• Burst read / write : Interleaved burst and linear burst sequence

• Fully registered inputs for flow through operation

• All registers triggered off positive clock edge

• LVTTL Compatible : All inputs and outputs

• Fast clock access time : 8.5 ns (100 MHz), 9 ns (90 MHz) (µPD4382321, µPD4382361)

9 ns (90 MHz), 10 ns (83 MHz) (µPD4382161, µPD4382181)

• Asynchronous output enable : /G

★

• Burst sequence selectable : MODE

• Sleep mode : ZZ (ZZ = Open or Low : Normal operation)

• Separate byte write enable :

/BW1 - /BW4 (µPD4382321, µPD4382361), /BW1 - /BW2 (µPD4382161, µPD4382181), /BWE

Global write enable : /GW

• Three chip enables for easy depth expansion

• Common I/O using three state outputs

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for

availability and additional information.

Document No. M14019EJ5V0DS00 (5th edition)

Date Published June 2000 NS CP(K)

Printed in Japan

The mark shows major revised points.

★

1999

12 3 4 5 6 7...24

中文翻译

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与UPD4382161GF-A10相关器件

型号	品牌	获取价格	描述	数据表
UPD4382161GF-A85	ETC	获取价格	x16 Fast Synchronous SRAM
UPD4382161GF-A85B	ETC	获取价格	x16 Fast Synchronous SRAM
UPD4382161GF-A90	ETC	获取价格	x16 Fast Synchronous SRAM
UPD4382161GF-A90B	ETC	获取价格	x16 Fast Synchronous SRAM
UPD4382162GF-A67	ETC	获取价格	x16 Fast Synchronous SRAM
UPD4382162GF-A67B	ETC	获取价格	x16 Fast Synchronous SRAM
UPD4382162GF-A75	ETC	获取价格	x16 Fast Synchronous SRAM
UPD4382162GF-A75B	ETC	获取价格	x16 Fast Synchronous SRAM
UPD4382181GF-A10	ETC	获取价格	x18 Fast Synchronous SRAM
UPD4382181GF-A85	ETC	获取价格	x18 Fast Synchronous SRAM

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