DATA SHEET
MOS INTEGRATED CIRCUIT
µPD30200, 30210
VR4300TM, VR4305TM, VR4310TM
64-BIT MICROPROCESSOR
DESCRIPTION
The µPD30200-100, 30200-133 (VR4300), 30200-80 (VR4305), and 30210 (VR4310) are high-performance, 64-
bit RISC (Reduced Instruction Set Computer) type VR SeriesTM microprocessors employing the RISC architecture
developed by MIPSTM Technologies Inc.
The VR4300, VR4305, and VR4310 are intended for the high-performance embedded device field and have 32-
bit system interface buses.
Detailed function descriptions are provided in the following user’s manual. Be sure to read this
manual before designing.
• VR4300, VR4305, VR4310 User’s Manual (U10504E)
FEATURES
• Employs 64-bit RISC MIPS architecture
• High-speed operation processing
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•
•
5-stage pipeline processing
High-speed execution of integer and floating-point operations
48 SPECint92, 36 SPECfp92, 106 MIPS, at 80 MHz operation (µPD30200-80)
60 SPECint92, 45 SPECfp92, 131 MIPS, at 100 MHz operation (µPD30200-100)
80 SPECint92, 60 SPECfp92, 177 MIPS at 133 MHz operation (µPD30200-133, µPD30210-133)
100 SPECint92, 75 SPECfp92, 221 MIPS at 167 MHz operation (µPD30210-167)
• Instruction set compatible with VR4000TM Series (conforms to MIPS-I/II/III)
• On-chip cache memory (Instruction: 16 Kbytes, Data: 8 Kbytes)
• 32-bit address/data multiplexed bus facilitating system design
• Low power consumption
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•
•
µPD30200-80: 1.5 W (TYP.) (at 80 MHz operation)
µPD30200-100, 30200-133: 1.8 W (TYP.) (at 100 MHz operation), 2.4 W (TYP.) (at 133 MHz operation)
µPD30210-×××: 1.9 W (TYP.) (at 133 MHz operation), 2.4 W (TYP.) (at 167 MHz operation)
• Supply voltage: 3.3 ± 0.3 V (µPD30200-80, 30200-100), 3.0 to 3.5 V (µPD30200-133, 30210-×××)
Unless otherwise specified, the VR4300 (µPD30200) is treated as the representative model throughout this document.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
The mark
shows major revised points.
Document No. U10116EJ7V0DS00 (7th edition)
Date Published November 2000 N CP(K)
Printed in Japan
1995, 1998
©
1994