PRELIMINARY DATA SHEET
3 V, SILICON MMIC 150 MHz
QUADRATURE MODULATOR
UPC8101GR
INTERNAL BLOCK DIAGRAM
FEATURES
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OPERATING FREQUENCY: 50 to 150 MHz
I/Q INPUT FREQUENCY RANGE: DC to 500 kHz
DIGITAL 90° PHASE SHIFTER
ALLOWABLE BIAS VOLTAGE: 2.7 to 5.5 V
POWER SAVE: "SLEEP" MODE
19
17
15
14
13
12
11
20
18
16
REG.
90˚
270˚
LPF
LPF
SMALL SIZE SSOP20 SURFACE MOUNT PACKAGE
TAPE AND REEL PACKAGING OPTION AVAILABLE
0˚
180˚
F/F
DESCRIPTION
The UPC8101GR is a Silicon Monolithic Integrated Circuit
(MMIC) which is manufactured using NEC's 20 GHz fT NESAT
III process. The Quadrature Modulator was designed for
digital mobile communications in general, and the CT2 band
requirements in particular. Operating on DC bias voltages as
low as 2.7 volts, this IC is ideal for handheld/portable designs.
1
2
4
5
3
6
7
8
9
10
11. VCC
1. LOCAL IN
2. LOCAL IN
3. GND
4. Q-BIAS
5. Q-BIAS
6. GND
7. Q-INPUT
8. Q-INPUT
9. GND
12. VENABLE
13. I-INPUT
14. I-INPUT
15. GND
16. I-BIAS
17. I-BIAS
18. GND
The UPC8101GR takes an external LO signal, and digitally
divides its frequency by two to generate the quadrature LO
required for the dual internal mixer circuits. These mixers also
receive external in-phase (I) and quadrature (Q) signals. The
up-converted outputs of the mixers are combined in a differ-
ential output amplifier. The resultant output signal is at fre-
quency of fLO/2 + fI/Q. Buffers are provided at the LO, I and Q
inputs, and filtering is provided between the digital frequency
divider and the mixers. The device can be powered down by
grounding the Enable pin.
19. N.C.
20. GND
10. IF OUTPUT
Note: N.C. = No Connection
NEC's stringent quality assurance and test procedures en-
sure the highest reliability and performance.
ELECTRICAL CHARACTERISTICS(TA = 25°C, LO PIN = -10 dBm, VENABLE 1.8 V, ZL = 50 Ω)
PART NUMBER
UPC8101GR
PACKAGE OUTLINE
S20 (SSOP 20)
VCC = 2.7 V
TYP
VCC = 5.5 V
TYP
SYMBOLS
PARAMETERS AND CONDITIONS
UNITS
MIN
MAX
MIN
MAX
ICC
CircuitCurrent
mA
mA
10
15
0.33
22
0.4
17
24.5
1.05
32
1.2
VENABLE ≤ 1.0 V
PSAT
LOLEAK
IM REJ
IM3
SaturatedOutputPower
dBm
dBm
dBc
dBc
KΩ
-16
28.5
500
-11
-49
37
-8
-13
28.5
500
-8
-39
38
-5
LO Leakage at IF Port (fLO/2)
Image Rejection at IF Port (fLO/2 - f I/Q)1
ThirdOrderIntermodulationDistortion1
I/Q Port Input Impedance
-37
-28
37
56
ZI/Q
1000
26
700
26
RLLO
RLIF
τ
LO Port Return Loss
dB
IF Port Return Loss
dB
21
21
Power Enable Response Time
Turn on
Turn off
µsec
µsec
1
1
5
3
1
1
5
3
VENABLE
PowerEnableControlVoltage
On
Off
V
V
1.8
5.5
1.0
1.8
5.5
1.0
Note:
1. fLO = 300.1 MHz, fI/Q = 36 kHz at VCC/2 + 1 Vp-p.
California Eastern Laboratories