Datasheet > 射频和微波 > 射频/微波调制器/解调器> UPC8101GR-E2

UPC8101GR-E2

更新时间： 2024-02-22 16:07:21

品牌	Logo	应用领域
日电电子 - NEC		射频调制器射频解调器微波调制器微波解调器射频和微波
页数	文件大小	规格书
3页	47K
描述
3 V, SILICON MMIC 150 MHz QUADRATURE MODULATOR

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数据手册

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UPC8101GR-E2 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
Reach Compliance Code：	unknown	风险等级：	5.31
Is Samacsys：	N	构造：	COMPONENT
最大输入功率 (CW)：	-7 dBm	JESD-609代码：	e0
调制技术：	I/Q	最大工作频率：	300 MHz
最小工作频率：	100 MHz	最高工作温度：	70 °C
最低工作温度：	-20 °C	射频/微波设备类型：	MODULATOR
端子面层：	Tin/Lead (Sn/Pb)	最大电压驻波比：	1.2
Base Number Matches：	1

UPC8101GR-E2 数据手册

PRELIMINARY DATA SHEET

3 V, SILICON MMIC 150 MHz

QUADRATURE MODULATOR

UPC8101GR

INTERNAL BLOCK DIAGRAM

FEATURES

•

OPERATING FREQUENCY: 50 to 150 MHz

I/Q INPUT FREQUENCY RANGE: DC to 500 kHz

DIGITAL 90° PHASE SHIFTER

ALLOWABLE BIAS VOLTAGE: 2.7 to 5.5 V

POWER SAVE: "SLEEP" MODE

REG.

90˚

270˚

LPF

SMALL SIZE SSOP20 SURFACE MOUNT PACKAGE

TAPE AND REEL PACKAGING OPTION AVAILABLE

0˚

180˚

F/F

DESCRIPTION

The UPC8101GR is a Silicon Monolithic Integrated Circuit

(MMIC) which is manufactured using NEC's 20 GHz f^TNESAT

III process. The Quadrature Modulator was designed for

digital mobile communications in general, and the CT2 band

requirements in particular. Operating on DC bias voltages as

low as 2.7 volts, this IC is ideal for handheld/portable designs.

11. VCC

1. LOCAL IN

2. LOCAL IN

3. GND

4. Q-BIAS

5. Q-BIAS

6. GND

7. Q-INPUT

8. Q-INPUT

9. GND

12. VENABLE

13. I-INPUT

14. I-INPUT

15. GND

16. I-BIAS

17. I-BIAS

18. GND

The UPC8101GR takes an external LO signal, and digitally

divides its frequency by two to generate the quadrature LO

required for the dual internal mixer circuits. These mixers also

receive external in-phase (I) and quadrature (Q) signals. The

up-converted outputs of the mixers are combined in a differ-

ential output amplifier. The resultant output signal is at fre-

quency of f^LO/2 + fI/Q. Buffers are provided at the LO, I and Q

inputs, and filtering is provided between the digital frequency

divider and the mixers. The device can be powered down by

grounding the Enable pin.

19. N.C.

20. GND

10. IF OUTPUT

Note: N.C. = No Connection

NEC's stringent quality assurance and test procedures en-

sure the highest reliability and performance.

ELECTRICAL CHARACTERISTICS(TA = 25°C, LO PIN = -10 dBm, VENABLE 1.8 V, ZL = 50 Ω)

PART NUMBER

UPC8101GR

PACKAGE OUTLINE

S20 (SSOP 20)

VCC = 2.7 V

TYP

VCC = 5.5 V

TYP

SYMBOLS

PARAMETERS AND CONDITIONS

UNITS

MIN

MAX

MIN

MAX

ICC

CircuitCurrent

0.33

0.4

24.5

1.05

1.2

VENABLE ≤ 1.0 V

PSAT

LOLEAK

IM REJ

IM3

SaturatedOutputPower

dBm

dBc

KΩ

-16

28.5

500

-11

-49

-8

-13

28.5

500

-8

-39

-5

LO Leakage at IF Port (fLO/2)

Image Rejection at IF Port (fLO/2 - f I/Q)¹

ThirdOrderIntermodulationDistortion¹

I/Q Port Input Impedance

-37

-28

ZI/Q

1000

700

RLLO

RLIF

LO Port Return Loss

IF Port Return Loss

Power Enable Response Time

Turn on

Turn off

µsec

VENABLE

PowerEnableControlVoltage

Off

1.8

5.5

1.0

1.8

5.5

1.0

Note:

1. fLO = 300.1 MHz, fI/Q = 36 kHz at VCC/2 + 1 Vp-p.

California Eastern Laboratories

12 3

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与UPC8101GR-E2相关器件

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UPC8102	NEC	RF AMPLIFIER IC FOR 150 MHz TO 330 MHz PAGER SYSTEM	获取价格
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