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UCC5630 PDF预览

UCC5630

更新时间: 2024-11-22 22:49:27
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德州仪器 - TI /
页数 文件大小 规格书
5页 61K
描述
Low Voltage Differential LVD/SE SCSI 9 Line Terminator

UCC5630 数据手册

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UCC5630  
Low Voltage Differential (LVD/SE) SCSI 9 Line Terminator  
FEATURES  
DESCRIPTION  
Auto Selection Multi-Mode Single  
Ended or Low Voltage Differential  
Termination  
The UCC5630 Multi-Mode Low Voltage Differential and Single Ended Ter-  
minator is both a single ended terminator and a low voltage differential ter-  
minator for the transition to the next generation SCSI Parallel Interface  
(SPI-2). The low voltage differential is a requirement for the higher speeds  
at a reasonable cost and is the only way to have adequate skew budgets.  
The transceivers can be incorporated into the controller, unlike SCSI high  
power differential (EIA485) which requires external transceivers. Low Volt-  
age differential is specified for Fast-40 and Fast-80, but has the potential of  
speeds up to Fast-320. The UCC5630 is SPI-2, SPI and Fast-20 compliant.  
Consult SSOP-36 and LQFP-48 Package Diagram for exact dimensions.  
2.7V to 5.25V Operation  
Differential Failsafe Bias  
Thermal Packaging for Low Junction  
Temperature and Better MTBF  
Master/Slave Inputs  
Supports Active Negation  
Standby (Disable Mode) 5µA  
3pF Channel Capacitance  
The UCC5630 can not be used with SCSI high voltage differential (HVD)  
EIA485. It will shut down when it sees high power differential to protect the  
bus. The pinning for high power differential is not the same as LVD or sin-  
gle ended and the bias voltage, current and power are also different for  
EIA485 differential.  
BLOCK DIAGRAM  
SOURCE ONLY FROM TRMPWR AND THE ENABLED TERMINATORS  
SOURCE 5 < 15mA  
SINK 200µA MAXIMUM (NOISE LOAD)  
OPEN CIRCUIT ON POWER OFF  
OR  
TRMPWR 36  
MSTR/SLV 19  
+V  
OPEN CIRCUIT IN A DISABLED  
TERMINATOR MODE  
DD  
REEF 1.3V  
20  
35  
1.3V ± –0.1V  
DIFFSENS  
HIPD  
2.2 > 1.9V  
0.7 > 0.6V  
DIFFB  
20k  
21  
34 LVD  
33 SE  
0.1µF  
LOW  
FREQUENCY  
FILTER  
110  
125  
SOURCE/SINK  
REGULATOR  
50Hz – 60Hz  
REF 2.7V  
+50mV TO +62.5mV  
52  
52  
REF 1.25V  
5
4
L1–  
L1+  
HIGH IMPEDANCE  
RECEIVER EVEN  
WITH POWER OFF  
HS/GND  
HS/GND  
8
9
110  
HS/GND 10  
HS/GND 26  
HS/GND 27  
HS/GND 28  
GND 18  
+50mV TO +62.5mV  
125  
52  
52  
32 L9–  
31 L9+  
SWITCHES UP ARE SINGLE  
ENDED SWITCHES DOWN ARE  
LOW VOLTAGE DIFFERENTIAL  
SE GND  
SWITCH  
DISCNCT 17  
REG  
1
MWP 36 PINOUT  
4.7µF  
UDG-98049  
Circuit Design Patented  
01/99  

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