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UCC27523_13

更新时间： 2024-02-29 16:15:13
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41页 1903K
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Dual 5-A High-Speed Low-Side Gate Driver

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UCC27523_13 数据手册

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UCC27523, UCC27524, UCC27525, UCC27526  
www.ti.com  
SLUSAQ3F –NOVEMBER 2011–REVISED MAY 2013  
Dual 5-A High-Speed Low-Side Gate Driver  
Check for Samples: UCC27523, UCC27524, UCC27525, UCC27526  
1
FEATURES  
APPLICATIONS  
2
•
•
•
•
•
Industry-Standard Pin Out  
•
•
•
•
Switch-Mode Power Supplies  
Two Independent Gate-Drive Channels  
5-A Peak Source and Sink-Drive Current  
Independent-Enable Function for Each Output  
DC-to-DC Converters  
Motor Control, Solar Power  
Gate Drive for Emerging Wide Band-Gap  
Power Devices such as GaN  
TTL and CMOS Compatible Logic Threshold  
Independent of Supply Voltage  
DESCRIPTION  
•
•
Hysteretic-Logic Thresholds for High Noise  
Immunity  
The UCC2752x family of devices are dual-channel  
high-speed low-side gate-driver devices capable of  
effectively driving MOSFET and IGBT power  
switches. Using a design that inherently minimizes  
shoot-through current, UCC2752x is capable of  
delivering high-peak current pulses of up to 5-A  
source and 5-A sink into capacitive loads along with  
rail-to-rail drive capability and extremely small  
propagation delay typically 13 ns. In addition, the  
drivers feature matched internal propagation delays  
between the two channels which are very well suited  
for applications requiring dual-gate drives with critical  
timing, such as synchronous rectifiers. This also  
enables connecting two channels in parallel to  
effectively increase current-drive capability or driving  
two switches in parallel with a single input signal. The  
input pin thresholds are based on TTL and CMOS  
compatible low-voltage logic, which is fixed and  
independent of the VDD supply voltage. Wide  
hysteresis between the high and low thresholds offers  
excellent noise immunity.  
Inputs and Enable Pin-Voltage Levels Not  
Restricted by VDD Pin Bias Supply Voltage  
•
•
4.5 to 18-V Single-Supply Range  
Outputs Held Low During VDD-UVLO, (ensures  
glitch-free operation at power-up and power-  
down)  
•
•
Fast Propagation Delays (13-ns typical)  
Fast Rise and Fall Times (7-ns and 6-ns  
typical)  
•
•
1-ns Typical Delay Matching Between 2-  
Channels  
Two Outputs are Paralleled for Higher Drive  
Current  
•
•
Outputs Held in LOW When Inputs Floating  
PDIP-8, SOIC-8, MSOP-8 PowerPAD™ and 3-  
mm × 3-mm WSON-8 Package Options  
•
Operating Temperature Range of –40°C to  
+140°C  
PRODUCT MATRIX  
One Inverting and One  
Non-Inverting Input  
Dual Input Configuration  
UCC27526  
Dual Inverting Inputs  
UCC27523  
Dual Non-Inverting Inputs  
UCC27524  
UCC27525  
INA-  
1
8
INA+  
ENA  
1
8
7
6
5
ENB  
ENA  
INA  
1
2
3
4
8
7
6
5
ENB  
ENA  
INA  
1
2
3
4
8
7
6
5
ENB  
INA  
GND  
INB  
2
3
4
OUTA  
VDD  
OUTA  
VDD  
OUTA  
VDD  
INB-  
GND  
2
3
4
7
6
5
INB+  
OUTA  
VDD  
GND  
INB  
GND  
INB  
OUTB  
OUTB  
OUTB  
OUTB  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
PowerPAD is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2011–2013, Texas Instruments Incorporated  
 
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