Datasheet > UCC27511A-Q1_15

UCC27511A-Q1_15

更新时间： 2022-02-26 11:36:26

品牌	Logo	应用领域
德州仪器 - TI		栅
页数	文件大小	规格书
31页	1245K
描述
Single-Channel High-Speed Low-Side Gate Driver With 4-A Peak Source and 8-A Peak Sink

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UCC27511A-Q1_15 数据手册

UCC27511A-Q1

SLVSCO2A –AUGUST 2014–REVISED SEPTEMBER 2014

www.ti.com

7.6 Switching Characteristics

V_DD= 12 V, T_A= T_J= –40°C to 140°C, 1-µF capacitor from V_DDto GND. Currents are positive into, negative out of the

specified terminal. See Figure 1, Figure 2, Figure 3, and Figure 4

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_DD= 12 V

C_(LOAD)= 1.8 nF, connected to

OUTH and OUTL pins tied together

t_r

Rise time⁽¹⁾

V_DD= 4.5 V

C_(LOAD)= 1.8 nF

V_DD= 12 V

C_(LOAD)= 1.8 nF, connected to

OUTH and OUTL pins tied together

t_f

Fall time⁽¹⁾

V_DD= 4.5 V

C_(LOAD)= 1.8 nF

V_DD= 12 V

5-V input pulse C_(LOAD)= 1.8 nF,

connected to OUTH and OUTL pins

tied together

t_d(1)

IN+ to output propagation delay⁽¹⁾

V_DD= 4.5 V

5-V input pulse C_(LOAD)= 1.8 nF,

connected to OUTH and OUTL pins

tied together

V_DD= 12 V

C_(LOAD)= 1.8 nF, connected to

OUTH and OUTL pins tied together

t_d(2)

IN– to output propagation delay⁽¹⁾

V_DD= 4.5 V

C_(LOAD)= 1.8 nF, connected to

OUTH and OUTL pins tied together

(1) See timing diagrams in Figure 1, Figure 2, Figure 3, and Figure 4.

High

INPUT

(IN+ pin)

Low

High

IN– pin

Low

90%

OUTPUT

10%

t_d(1)t_r

Figure 1. Non-Inverting Configuration

(PWM Input to IN+ pin (IN– Pin Tied to GND),

Output Represents OUTH and OUTL Pins Tied Together in the UCC27511A-Q1)

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