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UCC1583J PDF预览

UCC1583J

更新时间： 2024-11-04 20:08:11
品牌 Logo 应用领域
德州仪器 - TI 信息通信管理开关
页数 文件大小 规格书
10页 405K
描述
1.8A SWITCHING CONTROLLER, 500kHz SWITCHING FREQ-MAX, CDIP14, CERAMIC, DIP-14

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中文翻译

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UCC1583J 技术参数

是否Rohs认证：不符合生命周期：Obsolete
零件包装代码：DIP包装说明：CERAMIC, DIP-14
针数：14Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
Factory Lead Time：1 week风险等级：5.22
Is Samacsys：N模拟集成电路 - 其他类型：SWITCHING CONTROLLER
控制模式：CURRENT-MODE控制技术：PULSE WIDTH MODULATION
最大输入电压：14 V最小输入电压：10 V
标称输入电压：12 VJESD-30 代码：R-CDIP-T14
功能数量：1端子数量：14
最高工作温度：125 °C最低工作温度：-55 °C
最大输出电流：1.8 A封装主体材料：CERAMIC, METAL-SEALED COFIRED
封装代码：DIP封装等效代码：DIP14,.3
封装形状：RECTANGULAR封装形式：IN-LINE
峰值回流温度（摄氏度）：NOT SPECIFIED认证状态：Not Qualified
子类别：Switching Regulator or Controllers表面贴装：NO
切换器配置：BUCK最大切换频率：500 kHz
技术：BICMOS温度等级：MILITARY
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
Base Number Matches：1

UCC1583J 数据手册

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UCC1583  
UCC2583  
UCC3583  
Switch Mode Secondary Side Post Regulator  
FEATURES  
DESCRIPTION  
• Precision Secondary Side Post  
Regulation for Multiple Output Power  
Supplies  
The UCC3583 is a synchronizable secondary side post regulator for preci-  
sion regulation of the auxiliary outputs of multiple output power supplies. It  
contains a leading edge pulse width modulator, which generates the gate  
drive signal for a FET power switch connected in series with the rectifying  
diode. The turn-on of the power switch is delayed from the leading edge of  
the secondary power pulse to regulate the output voltage. The UCC3583  
contains a ramp generator slaved to the secondary power pulse, a voltage  
error amplifier, a current error amplifier, a PWM comparator and associ-  
ated logic, a gate driver, a precision reference, and protection circuitry.  
• Useful for Both Single Ended and  
Center Tapped Secondary Circuits  
• Ideal Replacement for Complex  
Magnetic Amplifier Regulated Circuits  
• Leading Edge Modulation  
The ramp discharge and termination of the gate drive signal are triggered  
by the synchronization pulse, typically derived from the falling edge of the  
transformer secondary voltage. The ramp starts charging again once its  
low threshold is reached. The gate drive signal is turned on when the ramp  
voltage exceeds the control voltage. This leading edge modulation tech-  
nique prevents instability when the UCC3583 is used in peak current mode  
primary controlled systems.  
• Does Not Require Gate Drive  
Transformer  
• High Frequency (>500kHz) Operation  
• Applicable for Wide Range of Output  
Voltages  
• High Current Gate Driver (0.5A  
The controller operates from a floating power supply referenced to the out-  
put voltage being controlled. It features an undervoltage lockout (UVLO)  
circuit, a soft start circuit, and an averaging current limit amplifier. The cur-  
rent limit can be programmed to be proportional to the output voltage, thus  
achieving foldback operation to minimize the dissipation under short circuit  
conditions.  
Sink/1.5A Source)  
• Average Current Limiting Loop  
(continued)  
TYPICAL APPLICATION AND BLOCK DIAGRAM  
UDG-96201-2  
Note: Pin connections shown for 14-pin packages.  
11/98  
1234567...10

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