Datasheet > UC5604PWP

UC5604PWP

更新时间： 2024-11-18 23:38:59

品牌	Logo	应用领域
其他 - ETC		/
页数	文件大小	规格书
5页	267K
描述
Terminator

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数据手册

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UC5604PWP 数据手册

UC5604

9-Line Low Capacitance SCSI Active Terminator

FEATURES

DESCRIPTION

•

Complies with SCSI, SCSI-2

Standards

The UC5604 provides 9 lines of active termination for a SCSI (Small Com-

puter Systems Interface) parallel bus. The SCSI standard recommends ac-

tive termination at both ends of the cable segment.

9pF Channel Capacitance during

Disconnect

The UC5604 provides a disconnect feature which, when opened or driven

high, will disconnect all terminating resistors and disable the regulator,

greatly reducing standby power. The output channels remain high imped-

ance even without Termpwr applied.

100µA Supply Current in

Disconnect Mode

•

Meets SCSI Hot Plugging Capability

The UC5604 is pin-for-pin compatible with its predecessor, the UC5603 - 9

line Active Terminator. The only functional difference between the UC5604

and UC5603 is the absence of the negative clamps. Parametrically, the

UC5604 has a 7% tolerance on impedance and current compared to a 3%

tolerance on the UC5603 and the sink current is reduced from 300mA to

40mA. Custom power packages are utilized to allow normal operation at

full power conditions (1.2 watts).

−300mA Sourcing Current for

Termination

•

+40mA Sinking Current for Active

Negation

Logic Command Disconnects all

Termination Lines

Internal circuit trimming is utilized, first to trim the impedance to a 7% toler-

ance, and then most importantly, to trim the output current to a 7% toler-

ance, as close to the max SCSI spec as possible, which maximizes noise

margin in fast SCSI operation.

•

Trimmed Termination Current to 7%

Trimmed Impedance to 7%

Current Limit and Thermal

Shutdown Protection

Other features include thermal shutdown and current limit.

This device is offered in low thermal resistance versions of the industry

standard 16 pin narrow body SOIC, 16 pin ZIP (zig-zag in line package)

and 24 pin TSSOP.

BLOCK DIAGRAM

UDG-94064

Circuit Design Patented

3/97

12 3 4 5

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