UC5603
9-Line SCSI Active Terminator
FEATURES
DESCRIPTION
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Complies with SCSI, SCSI-2 and
SPI-2 Standards
The UC5603 provides 9 lines of active termination for a SCSI (Small Comput-
ers Systems Interface) parallel bus. The SCSI standard recommends active
termination at both ends of the cable segment.
6pF Channel Capacitance during
Disconnect
The UC5603 provides a disconnect feature which, when opened or driven
high, will disconnect all terminating resistors, and disables the regulator;
greatly reducing standby power. The output channels remain high impedance
even without Termpwr applied. A low channel capacitance of 6pF allows units
at interim points of the bus to have little to no effect on the signal integrity.
100µA Supply Current in
Disconnect Mode
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Meets SCSI Hot Plugging
Functionally the UC5603 is similar to its predecessor, the UC5601 - 18 line
Active Terminator. Several electrical enhancements were incorporated in the
UC5603, such as a sink/source regulator output stage to accommodate all
signal lines at +5V, while the regulator remains at its nominal value, reduced
channel capacitance to 6pF typical, and as with the UC5601, custom power
packages are utilized to allow normal operation at full power conditions (1.2
watts).
-400mA Sourcing Current for
Termination
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+400mA Sinking Current for
Active Negation Drivers
Logic Command Disconnects all
Termination Lines
Trimmed Termination Current to
3%
Internal circuit trimming is utilized, first to trim the impedance to a 3% toler-
ance, and then most importantly, to trim the output current to a 3% tolerance,
as close to the max SCSI spec as possible, which maximizes noise margin in
fast SCSI operation.
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Trimmed Impedance to 3%
Negative Clamping on all Signal
Lines
Other features include negative clamping on all signal lines to protect exter-
nal circuitry from latch-up, thermal shutdown and current limit.
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Current Limit and Thermal
Shutdown Protection
This device is offered in low thermal resistance versions of the industry stand-
ard 16 pin narrow body SOIC, 16 pin ZIP (zig-zag in line package) and 24 pin
TSSOP.
BLOCK DIAGRAM
UDG-94049
Circuit Design Patented
3/97