Datasheet > UC3527AQTR

UC3527AQTR

更新时间： 2024-11-10 23:38:55

品牌	Logo	应用领域
其他 - ETC		开关控制器
页数	文件大小	规格书
8页	695K
描述
Voltage-Mode SMPS Controller

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中文翻译

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数据手册

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UC3527AQTR 数据手册

UC1525A/27A

UC2525A/27A

UC3525A/27A

Regulating Pulse Width Modulators

FEATURES

DESCRIPTION

•

8 to 35V Operation

The UC1525A/1527A series of pulse width modulator integrated circuits are de-

signed to offer improved performance and lowered external parts count when used

in designing all types of switching power supplies. The on-chip +5.1V reference is

trimmed to ±1% and the input common-mode range of the error amplifier includes

the reference voltage, eliminating external resistors. A sync input to the oscillator

allows multiple units to be slaved or a single unit to be synchronized to an external

system clock. A single resistor between the CT and the discharge terminals pro-

vides a wide range of dead-time adjustment. These devices also feature built-in

soft-start circuitry with only an external timing capacitor required. A shutdown termi-

nal controls both the soft-start circuitry and the output stages, providing instantane-

ous turn off through the PWM latch with pulsed shutdown, as well as soft-start

recycle with longer shutdown commands. These functions are also controlled by

an undervoltage lockout which keeps the outputs off and the soft-start capacitor

discharged for sub-normal input voltages. This lockout circuitry includes approxi-

mately 500mV of hysteresis for jitter-free operation. Another feature of these PWM

circuits is a latch following the comparator. Once a PWM pulse has been termi-

nated for any reason, the outputs will remain off for the duration of the period. The

latch is reset with each clock pulse. The output stages are totem-pole designs ca-

pable of sourcing or sinking in excess of 200mA. The UC1525A output stage fea-

tures NOR logic, giving a LOW output for an OFF state. The UC1527A utilizes OR

logic which results in a HIGH output level when OFF.

•

5.1V Reference Trimmed to

±1%

•

100Hz to 500kHz Oscillator

Range

Separate Oscillator Sync

Terminal

•

Adjustable Deadtime Control

Internal Soft-Start

Pulse-by-Pulse Shutdown

Input Undervoltage Lockout

with Hysteresis

•

Latching PWM to Prevent

Multiple Pulses

Dual Source/Sink Output

Drivers

BLOCK DIAGRAM

2/96

12 3 4 5 6 7 8

中文翻译

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