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UC2527BDW

更新时间： 2024-11-11 03:57:23
品牌 Logo 应用领域
德州仪器 - TI 开关脉冲光电二极管输出元件
页数 文件大小 规格书
14页 651K
描述
Regulating Pulse Width Modulators

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中文翻译

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UC2527BDW 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：SOIC包装说明：SOP, SOP16,.4
针数：16Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.84模拟集成电路 - 其他类型：SWITCHING CONTROLLER
控制模式：VOLTAGE-MODE控制技术：PULSE WIDTH MODULATION
最大输入电压：35 V最小输入电压：8 V
标称输入电压：20 VJESD-30 代码：R-PDSO-G16
长度：10.365 mm功能数量：1
端子数量：16最高工作温度：85 °C
最低工作温度：-40 °C最大输出电流：0.5 A
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP16,.4封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：NOT SPECIFIED
认证状态：Not Qualified座面最大高度：2.64 mm
子类别：Switching Regulator or Controllers表面贴装：YES
切换器配置：PUSH-PULL最大切换频率：500 kHz
技术：BIPOLAR温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7.5 mmBase Number Matches：1

UC2527BDW 数据手册

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application  
INFO  
UC1525B UC1527B  
UC2525B UC2527B  
UC3525B UC3527B  
available  
Regulating Pulse Width Modulators  
FEATURES  
DESCRIPTION  
• 8 to 35V Operation  
The UC1525B/1527B series of pulse width modulator integrated circuits  
are designed to offer improved performance and lowered external parts  
count when used in designing all types of switching power supplies. The  
on-chip +5.1V buried zener reference is trimmed to ±0.75% and the input  
common-mode range of the error amplifier includes the reference voltage,  
eliminating external resistors. A sync input to the oscillator allows multiple  
units to be slaved or a single unit to be synchronized to an external system  
clock. A single resistor between the CT and the discharge terminals provide  
a wide range of dead time adjustment. These devices also feature built-in  
soft-start circuitry with only an external timing capacitor required. A shut-  
down terminal controls both the soft-start circuitry and the output stages,  
providing instantaneous turn off through the PWM latch with pulsed shut-  
down, as well as soft-start recycle with longer shutdown commands. These  
functions are also controlled by an undervoltage lockout which keeps the  
outputs off and the soft-start capacitor discharged for sub-normal input volt-  
ages. This lockout circuitry includes approximately 500mV of hysteresis for  
jitter-free operation. Another feature of these PWM circuits is a latch follow-  
ing the comparator. Once a PWM pulse has been terminated for any rea-  
son, the outputs will remain off for the duration of the period. The latch is  
reset with each clock pulse. The output stages are totem-pole designs ca-  
pable of sourcing or sinking in excess of 200mA. The UC1525B output  
stage features NOR logic, giving a LOW output for an OFF state. The  
UC1527B utilizes OR logic which results in a HIGH output level when OFF.  
• 5.1V Buried Zener Reference  
Trimmed to ±0.75%  
• 100Hz to 500kHz Oscillator Range  
• Separate Oscillator Sync Terminal  
• Adjustable Deadtime Control  
• Internal Soft-Start  
• Pulse-by-Pulse Shutdown  
• Input Undervoltage Lockout with  
Hysteresis  
• Latching PWM to Prevent Multiple  
Pulses  
• Dual Source/Sink Output Drivers  
• Low Cross Conduction Output Stage  
• Tighter Reference Specifications  
BLOCK DIAGRAM  
UDG-95055  
SLUS376 JULY 1995  
1234567...14

中文翻译

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