UC1904
UC2904
UC3904
Precision Quad Supply and Line Monitor
FEATURES
DESCRIPTION
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Inputs for Monitoring Up to Four
Supply Voltages
The UC1904 Quad Supply Monitor will respond to under- and over-volt-
age conditions on up to four continuously monitored voltage levels. Four
independent positive voltages can be monitored or, alternatively, two of
the sense inputs are preset to monitor -5V and -12V supplies. The de-
vice also monitors Over-Current and Line Sense inputs, both with preci-
sion input thresholds.
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Two Inputs Preset for -5V and -12V
Monitoring, or Programmable
Positive Levels
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Precision 2.5V Reference
Four open collector outputs on the UC1904 give the following re-
sponses: 1. The OV/OC output is a latched over-voltage, or over-current
response. 2. A Power Good signal responds low with any fault detection
– on power-up a programmable delay is used to hold this output low for
a system Power On Reset signal. 3. The PWRW output responds only to
a Line Sense input, for early warning of power failures. 4. The last open
collector, the ON/OFF output, generates a delayed supply OFF control
signal in response to an OFF input command, under-voltage condition,
or line fault detection.
Separate Inputs for Over-Current and
Line Fault Sensing
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Adjustable Under- to Over-Voltage
Fault Windows
Latched Over-Voltage and
Over-Current Output
Power Good and Power Warning
Outputs
The OV-UV fault window is adjustable with a programming input. The
thresholds are centered around the precision 2.5V reference, with a
scaled hysteresis for precise, glitch free operation. In the positive mode
of operation, the fault windows at each of the sense inputs can be inde-
pendently scaled using external resistors and the 2.5V reference output.
An Auto Restart function couples with the under-voltage and line sens-
ing circuits to allow controlled power supply start-up and shutdown.
Auto Restart Function with ON/OFF
Control, and Programmable Delay
Programmable Pwr On Reset Delay
This device will operate over a supply range of 4.75V to 18V. The device
is available in a DIP, SOIC, or PLCC outline. This device is ESD pro-
tected on all pins.
BLOCK DIAGRAM
Note: Pin Numbers refer to J, N, and DW Packages.
4/97