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U631H16DC35 PDF预览

U631H16DC35

更新时间: 2024-11-08 22:41:51
品牌 Logo 应用领域
其他 - ETC 静态存储器
页数 文件大小 规格书
12页 276K
描述
SOFTSTORE 2K X 8 NVSRAM

U631H16DC35 数据手册

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U631H16  
SoftStore 2K x 8 nvSRAM  
Packages: PDIP28 (300 mil)  
PDIP28 (600 mil)  
Data transfers from the SRAM to  
the EEPROM (the STORE opera-  
tion), or from the EEPROM to the  
SRAM (the RECALL ) operation)  
are initiated through software  
sequences.  
The U631H16 combines the high  
performance and ease of use of a  
fast SRAM with nonvolatile data  
integrity.  
Features  
SOP28 (300 mil)  
SOP24 (300 mil)  
High-performance CMOS non-  
volatile static RAM 2048 x 8 bits  
25, 35 and 45 ns Access Times  
12, 20 and 25 ns Output Enable  
Access Times  
Software STORE Initiation  
(STORE Cycle Time < 10 ms)  
Automatic STORE Timing  
105 STORE cycles to EEPROM  
10 years data retention in  
EEPROM  
Automatic RECALL on Power Up  
Software RECALL Initiation  
(RECALL Cycle Time < 20 µs)  
Unlimited RECALL cycles from  
EEPROM  
Description  
The U631H16 has two separate  
modes of operation: SRAM mode  
and nonvolatile mode. In SRAM  
mode, the memory operates as an  
ordinary static RAM. In nonvolatile  
operation, data is transferred in  
parallel from SRAM to EEPROM or  
from EEPROM to SRAM. In this  
mode SRAM functions are disab-  
led.  
Once a STORE cycle is initiated,  
further input or output are disabled  
until the cycle is completed.  
Because a sequence of addresses  
is used for STORE initiation, it is  
important that no other read or write  
accesses intervene in the sequence  
or the sequence will be aborted.  
Internally, RECALL is a two step  
procedure. First, the SRAM data is  
cleared and second, the nonvolatile  
information is transferred into the  
SRAM cells.  
The RECALL operation in no way  
alters the data in the EEPROM  
cells. The nonvolatile data can be  
recalled an unlimited number of  
times.  
The U631H16 is a fast static RAM  
(25, 35, 45 ns), with a nonvolatile  
Unlimited Read and Write to  
SRAM  
Single 5 V ± 10 % Operation  
Operating temperature ranges:  
0 to 70 °C  
electrically  
erasable  
PROM  
(EEPROM) element incorporated  
in each static memory cell. The  
SRAM can be read and written an  
unlimited number of times, while  
independent nonvolatile data resi-  
des in EEPROM.  
-40 to 85 °C  
CECC 90000 Quality Standard  
ESD characterization according  
MIL STD 883C M3015.7-HBM  
(classification see IC Code  
Numbers)  
Pin Configuration  
Pin Description  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
1
VCC  
W
n.c.  
n.c.  
A7  
1
2
A7  
A6  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
VCC  
A8  
2
3
n.c.  
A8  
Signal Name Signal Description  
3
A5  
4
A6  
A9  
A0 - A10  
Address Inputs  
Data In/Out  
4
A4  
5
A5  
A9  
W
5
6
A3  
DQ0 - DQ7  
A4  
n.c.  
G
G
PDIP  
SOP  
28  
6
7
A2  
A3  
A10  
E
SOP  
24  
Chip Enable  
E
7
8
A1  
A2  
A10  
E
Output Enable  
Write Enable  
Power Supply Voltage  
Ground  
G
8
9
A0  
A1  
DQ7  
DQ6  
DQ5  
DQ4  
DQ3  
W
9
10  
11  
12  
13  
14  
DQ0  
DQ1  
DQ2  
VSS  
A0  
DQ7  
DQ6  
DQ5  
DQ4  
DQ3  
VCC  
VSS  
10  
11  
12  
DQ0  
DQ1  
DQ2  
VSS  
17  
16  
15  
Top View  
Top View  
1
December 12, 1997  

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