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U62256ASC07LL PDF预览

U62256ASC07LL

更新时间: 2024-11-07 05:16:03
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器光电二极管
页数 文件大小 规格书
9页 79K
描述
Standard SRAM, 32KX8, 70ns, CMOS, PDSO28, 0.330 INCH, SOP-28

U62256ASC07LL 数据手册

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U62256A  
Standard 32K x 8 SRAM  
Description  
Features  
falling edge of W, or by the rising  
edge of E, respectively.  
F 32768x8 bit static CMOS RAM  
F Access times 70 ns, 100 ns  
F Common data inputs and  
data outputs  
F Three-state outputs  
F Typ. operating supply current  
70 ns: 50 mA  
The U62256A is a static RAM  
manufactured using a CMOS pro-  
cess technology with the following  
operating modes:  
Data retention is guaranteed down  
to 2 V. With the exception of E, all  
inputs consist of NOR gates, so  
that no pull-up/pull-down resistors  
are required.  
- Read  
- Write  
- Standby  
- Data Retention  
The memory array is based on a  
6-transistor cell.  
100 ns: 40 mA  
F TTL/CMOS-compatible  
F Automatical reduction of power  
dissipation in long Read Cycles  
The circuit is activated by the fal-  
ling edge of E. The address and  
control inputs open simultaneously.  
According to the information of W  
and G, the data inputs, or outputs,  
are active. In a Read cycle, the  
data outputs are activated by the  
falling edge of G, afterwards the  
data word read will be available at  
the outputs DQ0-DQ7. After the  
address change, the data outputs  
go High-Z until the new information  
read is available. The data outputs  
have not preferred state.  
+
F Power supply voltage 5 V 10 %  
F Operating temperature ranges  
0 to 70 °C  
-40 to 85 °C  
F CECC 90000 Quality Standard  
F ESD protection > 2000 V  
(MIL STD 883C M3015.7)  
F Latch-up immunity >100 mA  
F Package: SOP28 (330 mil)  
The Read cycle is finished by the  
Pin Configuration  
Pin Description  
1
VCC  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
A14  
A12  
A7  
2
W
3
A13  
A8  
4
A6  
Signal Name Signal Description  
5
A9  
A5  
A0 - A14  
Address Inputs  
Data In/Out  
6
A11  
A4  
DQ0 - DQ7  
7
A3  
G
Chip Enable  
SOP  
E
8
A10  
A2  
Output Enable  
Write Enable  
Power Supply Voltage  
Ground  
G
9
A1  
E
W
DQ7  
10  
11  
12  
13  
14  
A0  
VCC  
VSS  
DQ6  
DQ5  
DQ4  
DQ3  
DQ0  
DQ1  
DQ2  
VSS  
Top View  
August 01, 2002  
1

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