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U2781B-MFSG3 PDF预览

U2781B-MFSG3

更新时间: 2024-11-25 19:53:47
品牌 Logo 应用领域
爱特美尔 - ATMEL 光电二极管
页数 文件大小 规格书
10页 79K
描述
PLL Frequency Synthesizer, PDSO20, SSO-20

U2781B-MFSG3 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SSOP包装说明:SSOP, SSOP20,.25
针数:20Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.8
其他特性:PROGRAMMABLE 64/65 OR 128/129 PRESCALER模拟集成电路 - 其他类型:PLL FREQUENCY SYNTHESIZER
JESD-30 代码:R-PDSO-G20JESD-609代码:e0
长度:6.625 mm功能数量:1
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装等效代码:SSOP20,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
电源:3/5 V认证状态:Not Qualified
子类别:PLL or Frequency Synthesis Circuits最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):2.7 V标称供电电压 (Vsup):3 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
宽度:4.4 mmBase Number Matches:1

U2781B-MFSG3 数据手册

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U2781B  
Frequency Synthesizer  
Description  
The programmable frequency synthesizer IC U2781B for device a perfect choice for cordless phones and handheld  
µP-controlled applications is realized with Atmel cellular radio sets up to 1.1 GHz.  
Wireless & Microcontrollers’ advanced UHF process  
which is very suitable for combinations of fast ECL logic  
Electrostatic sensitive device.  
2
and low-current I L logic. The benefits are high input  
Observe precautions for handling.  
sensitivity combined with low power consumption and  
therefore small packages (SSO20). This makes the  
FD eVaetruyrloews current consumption (typ. 3 V/ 5 mA)  
Benefits  
D Very low current consumption extends talk time  
D Supply-voltage range: 2.7 to 5.5 V  
D Max. input frequency: 1.1 GHz  
D Few external components and SSO package save costs  
and space  
D Programmable prescaler 64/ 65 or 128/ 129  
D Controlled by 3-wire bus with f  
up to 500 kHz  
clock  
D Status output for PLL lock/ unlock condition  
D Very fast phase detector  
D SSO20 package  
D ESD protection in accordance with MIL-STD. 883  
method 3015 class 2  
Block Diagram  
1
14-bit  
reference counter  
Osci  
Oscillator  
Mo  
Osco  
17  
3
5
7
LDo  
V
S
8
4
15-bit latch  
V
GND  
SCP  
Clock  
Data  
11  
13  
14  
1-bit latch  
Phase  
18-bit  
shift register  
Charge  
pump  
CP  
PS  
load control  
detector  
6
Enable  
18-bit latch  
15  
Prescaler  
64/65  
11-bit  
7-bit  
swallow  
RFi  
main  
10  
U2781B  
128/129  
counter  
counter  
Figure 1. Block diagram  
Rev. A4, 11-Sep-00  
1 (10)  

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