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TXD0A

更新时间: 2024-11-06 01:23:55
品牌 Logo 应用领域
松下 - PANASONIC 微控制器
页数 文件大小 规格书
30页 400K
描述
8-bit Single-chip Microcontroller

TXD0A 数据手册

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MN101EF93G  
8-bit Single-chip Microcontroller  
PubNo. 21693-013E  
1.1 Overview  
1.1.1  
Overview  
The MN101E series of 8-bit single-chip microcomputers (the memory expansion version of MN101C series)  
incorporate multiple types of peripheral functions. This chip series is well suited for camera, TV, CD, printer, tele-  
phone, home appliance, PPC, fax machine, music instrument and other applications.  
This LSI brings to embedded microcomputer applications flexible, optimized hardware configurations and a sim-  
ple efficient instruction set. MN101EF93G have an internal 128 KB of ROM and 6 KB of RAM. Peripheral func-  
tions include 5 external interrupts, including NMI, 9 timer counters, 4 types of serial interfaces, A/D converter,  
watchdog timer and buzzer output. The system configuration is suitable for system control microcontroller.  
With 3 oscillation systems (internal frequency: 16 MHz, high-speed crystal/ceramic frequency: max. 10 MHz,  
low-speed crystal/ceramic frequency: 32.768 kHz) contained on the chip, the system clock can be switched to  
high-speed frequency input (NORMAL mode) or PLL input (PLL mode), or low-speed frequency input (SLOW  
mode). The system clock is generated by dividing the oscillation clock or PLL clock. The best operation clock for  
the system can be selected by switching its frequency ratio by programming. High speed mode has NORMAL  
mode which is based on the clock dividing fpll, (fpll is generated by original oscillation and PLL), by 2 (fpll/2),  
and the double speed mode which is based on the clock not dividing fpll.  
A machine cycle (minimum instruction execution time) in NORMAL mode is 200 ns when the original oscillation  
fosc is 10 MHz (PLL is not used). A machine cycle in the double speed mode, in which the CPU operates on the  
same clock as the external clock, is 100 ns when fosc is 10 MHz. A machine cycle in the PLL mode is 50 ns (max-  
imum).  
1.1.2  
Product Summary  
This manual describes the following model.  
Table:1.1.1 Product Summary  
Model  
ROM Size RAM Size  
128 KB 6 KB  
Classification  
Package  
MN101EF93G  
Flash EEPROM version 80 Pin LQFP  
Publication date: February 2015  
1

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