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TVP3703-135CFN PDF预览

TVP3703-135CFN

更新时间: 2024-10-30 15:55:15
品牌 Logo 应用领域
德州仪器 - TI 外围集成电路
页数 文件大小 规格书
21页 293K
描述
Video Interface Palette Extract 68-PLCC 0 to 70

TVP3703-135CFN 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Obsolete零件包装代码:LCC
包装说明:PLASTIC, LCC-68针数:68
Reach Compliance Code:not_compliantHTS代码:8542.31.00.01
Factory Lead Time:1 week风险等级:5.72
Is Samacsys:N地址总线宽度:3
显示配置:1600 X 1280 PIXELS外部数据总线宽度:8
JESD-30 代码:S-PQCC-J68长度:24.2316 mm
端子数量:68最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified座面最大高度:4.57 mm
最大供电电压:5.25 V最小供电电压:4.75 V
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:24.2316 mmuPs/uCs/外围集成电路类型:DISPLAY CONTROLLER, PALETTE DAC
Base Number Matches:1

TVP3703-135CFN 数据手册

 浏览型号TVP3703-135CFN的Datasheet PDF文件第2页浏览型号TVP3703-135CFN的Datasheet PDF文件第3页浏览型号TVP3703-135CFN的Datasheet PDF文件第4页浏览型号TVP3703-135CFN的Datasheet PDF文件第5页浏览型号TVP3703-135CFN的Datasheet PDF文件第6页浏览型号TVP3703-135CFN的Datasheet PDF文件第7页 
TVP3703  
VIDEO INTERFACE PALETTE  
TRUE-COLOR CMOS RAMDAC  
SLAS100 – MARCH 1996  
Fully Integrated Dual Clock Synthesizer  
On-Chip PLL Clock Reference Requires  
and 16-Bit Pixel Port True-Color RAMDAC  
Single External Crystal  
Two Phase-Locked-Loop (PLL)  
Synthesizers Provide Independently  
Controlled Video and Memory Clock  
Outputs  
16-Bit Pixel Port Supports VGA High-Color  
and True-Color Standards Up to 170 MHz  
Programmable Power-Down Features  
On-Chip Cyclic Redundancy Check (CRC)  
Functionally Interchangeable with STG1703  
Test  
description  
The TVP3703 is a super video graphics array (SVGA) compatible, true-color CMOS RAMDAC with integrated  
clock synthesizers that can provide the memory and pixel clock signals for a PC graphics subsystem. The video  
clock can be one of two VGA base frequencies or fourteen Video Electronics Standards Association (VESA)  
standard frequencies which can also be reprogrammed through the standard micro port interface.  
The memory clock output is also user programmable at frequencies up to 80 MHz. The pixel modes supported  
by the TVP3703 include:  
Serializing 16-bit pixel port providing 170 MHz, 8-bit and 73 MHz, 24-bit packed pixel modes using an  
internal PLL  
16-bit pixel port providing faster, high-color/true-color operation up to the 110 MHz sampling rate  
8-bit pixel port providing standard SVGA and high-color/true-color modes up to the 110 MHz sampling rate  
The 68 terminal FN package is designed to be interchangeable with the STG1703.  
FN PACKAGE  
(TOP VIEW)  
9
8
7
6 5 4 3 2 1 68 67 66 65 64 63 62 61  
GND  
BLANK  
D0  
10  
60 GND  
59 P7  
11  
12  
13  
14  
15  
16  
17  
58  
P6  
P5  
P4  
P3  
P2  
P1  
P0  
REF  
RS2  
COMP  
RSET  
VS3  
VS2  
VS1  
VS0  
D1  
D2  
D3  
D4  
57  
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
D5  
D6 18  
D7 19  
WR 20  
21  
22  
23  
24  
25  
26  
RS0  
RS1  
P14  
PIXMIX  
P15  
NC  
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43  
NC – No internal connection  
Copyright 1996, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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