Datasheet > TSXPC740AVGSB/Q10LE

TSXPC740AVGSB/Q10LE

更新时间： 2023-02-26 14:35:49

品牌	Logo	应用领域
爱特美尔 - ATMEL		/
页数	文件大小	规格书
42页	365K
描述
RISC Microprocessor, 32-Bit, 233MHz, CMOS, CBGA255, 21 X 21 MM, 4 MM HEIGHT, 1.27 MM PITCH, CERAMIC, CGA-255

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TSPC750A/740A

1.2. Features

ExeptL2cacheinterfacethatisnotsupportedbythePowerPCversion, themajorfeaturesimplementatedinthePowerPC750Aarchi-

tecture are as follow:

•

Level 2 (L2) cache interface (not implemented on TSPC740A)

— Internal L2 cache controller and 4K–entry

tags; external data SRAMs

— 64–byte (256K/512K) and 128–byte

(1–Mbyte) sectored line size

— Supports flow–through (reg–buf)

synchronous burst SRAMs, pipelined

(reg–reg) synchronous burst SRAMs, and

pipelined (reg–reg) late–write

— 256K, 512K, and 1 Mbyte 2–way set

associative L2 cache support

— Copy–back or write–through data cache

(on a page basis, or for all L2)

synchronous burst SRAMs

— Core–to–L2 frequency divisors of ÷1, ÷1.5, ÷2, ÷2.5, and ÷3 supported

•

Branch processing unit

— Four instructions fetched per clock

— One branch processed per cycle (plus resolving 2 speculations)

— Up to 1 speculative stream in execution, 1 additional speculative stream in fetch

— 512–entry branch history table (BHT) for dynamic prediction

— 64–entry, 4–way set associative branch target instruction cache (BTIC) to minimize branch delay slots

Dispatch unit

•

— Full hardware detection of dependencies (resolved in the execution units)

— Dispatch two instructions to six independent units (system, branch, load/store, fixed–point unit 1,

fixed–point unit 2, or floating–point)

— Serialization control (predispatch, postdispatch, execution serialization)

Load/store unit

— One cycle load or store cache access (byte, half–word, word, double–word)

— Effective address generation

— Hits under misses (one outstanding miss)

— Single–cycle misaligned access within double word boundary

— Alignment, zero padding, sign extend for integer register file

— Floating–point internal format conversion (alignment, normalization)

— Sequencing for load/store multiples and string operations

— Store gathering

— Cache and TLB instructions

— Big– and little–endian byte addressing supported

— Misaligned little–endian support in hardware

Fixed–point units

•

— Fixed–point unit 1 (FXU1)—multiply, divide, shift, rotate, arithmetic, logical

— Fixed–point unit 2 (FXU2)—shift, rotate, arithmetic, logical

— Single–cycle arithmetic, shift, rotate, logical

— Multiply and divide support (multi–cycle)

— Early out multiply

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与TSXPC740AVGSB/Q10LE相关器件

型号	品牌	描述	获取价格	数据表
TSXPC740AVGSB/Q12LE	ATMEL	RISC Microprocessor, 32-Bit, 266MHz, CMOS, CBGA255, 21 X 21 MM, 4 MM HEIGHT, 1.27 MM PITCH	获取价格
TSXPC740AVGSB/T10LE	ATMEL	RISC Microprocessor, 32-Bit, 233MHz, CMOS, CBGA255, 21 X 21 MM, 4 MM HEIGHT, 1.27 MM PITCH	获取价格
TSXPC740AVGSB/T10LH	ATMEL	RISC Microprocessor, 32-Bit, 233MHz, CMOS, CBGA255, 21 X 21 MM, 4 MM HEIGHT, 1.27 MM PITCH	获取价格
TSXPC740AVGSB/T8LE	ATMEL	RISC Microprocessor, 32-Bit, 200MHz, CMOS, CBGA255, 21 X 21 MM, 4 MM HEIGHT, 1.27 MM PITCH	获取价格
TSXPC740AVGSB/T8LH	ATMEL	RISC Microprocessor, 32-Bit, 200MHz, CMOS, CBGA255, 21 X 21 MM, 4 MM HEIGHT, 1.27 MM PITCH	获取价格
TSXPC740AVGSU/T10LE	ATMEL	RISC Microprocessor, 32-Bit, 233MHz, CMOS, CBGA255, 21 X 21 MM, 4 MM HEIGHT, 1.27 MM PITCH	获取价格

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