Datasheet > TSXPC750ACVIP233DE

TSXPC750ACVIP233DE

更新时间： 2024-01-27 14:33:50

品牌	Logo	应用领域
爱特美尔 - ATMEL		PC 外围集成电路
页数	文件大小	规格书
17页	209K
描述
RISC Microprocessor, 32-Bit, 233MHz, CMOS, 2.54 MM PITCH, PCM, PGA-288

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技术参数
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TSXPC750ACVIP233DE 技术参数

生命周期：	Obsolete	零件包装代码：	PGA
包装说明：	,	针数：	288
Reach Compliance Code：	unknown	ECCN代码：	3A001.A.2.C
HTS代码：	8542.31.00.01	风险等级：	5.84
地址总线宽度：	32	位大小：	32
边界扫描：	YES	外部数据总线宽度：	64
集成缓存：	YES	JESD-30 代码：	R-XXMA-P288
端子数量：	288	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	UNSPECIFIED
封装形状：	RECTANGULAR	封装形式：	MICROELECTRONIC ASSEMBLY
认证状态：	Not Qualified	速度：	233 MHz
最大供电电压：	2.73 V	最小供电电压：	2.47 V
标称供电电压：	2.6 V	表面贴装：	NO
技术：	CMOS	温度等级：	INDUSTRIAL
端子形式：	PIN/PEG	端子位置：	UNSPECIFIED
uPs/uCs/外围集成电路类型：	MICROPROCESSOR, RISC	Base Number Matches：	1

TSXPC750ACVIP233DE 数据手册

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TSPC750IP

Processor and Cache Module

DESCRIPTION

The Processor and Cache Module (PCM) is a 17 x 17 pin grid

array (PGA) circuit assembly which combines a PowerPCt

microprocessor and SRAM components into a CPU subsys-

tem. The PCM provides a standard mechanical, electrical, and

functional interface which can be socketed on a computer sys-

tem board and allows many combinations of processors and

optional components to be easily interchanged. This docu-

ment describes the general characteristics for a module con-

sisting of a single PowerPCt microprocessor and two SRAM

devices for L2 cache. The PCM packaging and PGA signal

definition also accomodates single processors without SRAM,

and multiple processors.

The PCM consists of an epoxy–glass (FR4) substrate which

adapts a processor in a ceramic ball grid array (CBGA) pac-

kage with 50 mil spacing to a 288–pin PGA with 100 mil spac-

ing that can be easily socketed and hence, easily upgraded.

The FR4 substrate can be extended beyond the area of the 17

x 17 pin grid array to provide an interconnect area for SRAM

components configured as closely coupled L2 cache. The

resulting PCM provides numerous flexible configurations of

processor and cache for various price/performance system

designs.

FR4 PCM on PGA 288 Interposer

60x Address

L2 Addr

L2–Cache

Memory

Chips

60x Data

TSPC750

L2 Data

60x Control

L2 Control

Processor

PLL_CFG

General

Support

Circuits

VID

PID

Simplified Block Diagram

1/17

April 1999

12 3 4 5 6 7...17

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