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TSXPC740AVGSB/Q12LE PDF预览

TSXPC740AVGSB/Q12LE

更新时间: 2024-01-27 20:51:07
品牌 Logo 应用领域
爱特美尔 - ATMEL 时钟外围集成电路
页数 文件大小 规格书
2页 169K
描述
RISC Microprocessor, 32-Bit, 266MHz, CMOS, CBGA255, 21 X 21 MM, 4 MM HEIGHT, 1.27 MM PITCH, CERAMIC, CGA-255

TSXPC740AVGSB/Q12LE 技术参数

生命周期:Obsolete零件包装代码:CGA
包装说明:CGA,针数:255
Reach Compliance Code:unknownECCN代码:3A001.A.2.C
HTS代码:8542.31.00.01风险等级:5.84
地址总线宽度:32位大小:32
边界扫描:YES最大时钟频率:83.3 MHz
外部数据总线宽度:64格式:FLOATING POINT
集成缓存:YESJESD-30 代码:S-CBGA-X255
长度:21 mm低功率模式:YES
端子数量:255封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:CGA封装形状:SQUARE
封装形式:GRID ARRAY认证状态:Not Qualified
筛选级别:MIL-STD-883 Class B速度:266 MHz
最大供电电压:2.7 V最小供电电压:2.5 V
标称供电电压:2.6 V表面贴装:YES
技术:CMOS端子形式:UNSPECIFIED
端子节距:1.27 mm端子位置:BOTTOM
宽度:21 mmuPs/uCs/外围集成电路类型:MICROPROCESSOR, RISC
Base Number Matches:1

TSXPC740AVGSB/Q12LE 数据手册

 浏览型号TSXPC740AVGSB/Q12LE的Datasheet PDF文件第2页 
PC740A/PC750AFS - Rev.1 – 01/11  
PC740A and 750APowerPC™ Microprocessors  
Fact Sheet  
The PowerPC 750 and PowerPC740 microprocessors are low-power 32-bit implementations of the PowerPC Reduced  
Instruction Set Computer (RISC) architecture. The PowerPC 750 and the PowerPC 740 micro-processors differ only in that  
the PowerPC 750 features a dedicated L2 cache interface with on-chip L2 tags.  
Both are software -compatible and bus-compatible with the PowerPC603eTM micro -processor families, and the PowerPC  
740 is pin-compatible as well. PowerPC 750/740 micro-processors are fully JTAG-compliant.  
PC740/750 Main Features  
n
Six independent execution units :  
- Two integer units  
- Floating-point unit  
- Branch processing unit  
- Load/store unit  
- System register unit  
n
Cache and MMU Support  
- 32-Kbytes, physically-addressed instruction and data cache  
- 8-way set -associative  
- Dedicated L2 cache interface with on-chip L2 tags (PC750, only)  
- Separate Instruction and Data MMUs  
- Virtual memory support up to 4 Petabytes (252)  
- Real memory support up to 4 Gigabytes (252)  
- 128-entry instruction and data TLBs  
Completion  
Unit  
Branch  
Unit  
Dispatch  
Unit  
Gen  
Reg  
File  
FPU  
Reg  
File  
Floating  
Point  
Unit  
Gen  
Re-  
name  
Load/  
Store  
Unit  
Integer  
Unit  
I MMU  
D MMU  
Inst. Cache  
Data Cache  
L2  
tags  
Bus Interface Unit  
64bit  
Data  
32bit  
Address  
L2 Cache  
Port (750 only)  
System Bus  
L2 Data Bus  

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