Features
• 12.4 SPECint95, 8.4 SPECfp95 at 266 MHz (TSPC750A) with 1 MB L2 at 133 MHz
• 11.5 SPECint95, 6.9 SPECfp95 at 266 MHz (TSPC740A)
• 488 MIPS at 266 MHz
• Selectable Bus Clock (11 CPU Bus Dividers up to 8x)
• PD Typical 4.2 W at 200 MHz, Full Operating Conditions
• Nap, Doze and Sleep Modes for Power Savings
• Superscalar (3 Instructions per Clock Cycle)
• 4-GByte Direct Addressing Range
• 64-bit Data and 32-bit Address Bus Interface
• 32 KB Instruction and Data Cache
• Six Independent Execution Units and Two Register Files
• Write-back and Write-through Operations
• fint max = 266 MHz
PowerPC
750A/740A RISC
Microprocessor
Family PID8t-
750A/740A
• fbus max = 83.3 MHz
• Compatible CMOS Input / TTL Output
Description
The TSPC750A and TSPC740A microprocessor (after named 750A/740A) are low-
power implementations of the PowerPC Reduced Instruction Set Computer (RISC)
architecture.
Specification
The 750A/740A microprocessors’ designs are superscalar, capable of issuing three
instructions per clock cycle into six independent execution units.
TSPC750A/740A
The 740A/750A microprocessors use a 2.6/3.3V CMOS process technology and
maintain full interface compatibility with TTL devices.
The 750A/740A provide four software controllable power-saving modes and a thermal
assist unit management.
The 750A/740A microprocessors have separate 32K byte, physically-addressed
instruction and data caches and differ only in that the 750A features a dedicated L2
cache interface with L2 on-chip tags.
Both are software and bus-compatible with the PowerPC 603™ and PowerPC 604™
families, and are fully JTAG compliant.
The TSPC740A microprocessor is pin compatible with the TSPC603e family.
GS suffix
G suffix
CI-CBGA255 and CI-CBGA360
CBGA255 and CBGA360
Ceramic Ball Grid Array
Ceramic Ball Grid Array
with Solder Column Interposer (SCI)
Rev. 2128A–HIREL–01/02
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