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TSPC740AVGSB/Q10LH PDF预览

TSPC740AVGSB/Q10LH

更新时间: 2024-11-29 19:42:47
品牌 Logo 应用领域
爱特美尔 - ATMEL 时钟ATM异步传输模式外围集成电路
页数 文件大小 规格书
42页 365K
描述
RISC Microprocessor, 32-Bit, 233MHz, CMOS, CBGA255, 21 X 21 MM, 4 MM HEIGHT, 1.27 MM PITCH, CERAMIC, CGA-255

TSPC740AVGSB/Q10LH 技术参数

生命周期:Obsolete零件包装代码:CGA
包装说明:CGA,针数:255
Reach Compliance Code:unknownECCN代码:3A001.A.2.C
HTS代码:8542.31.00.01风险等级:5.84
地址总线宽度:32位大小:32
边界扫描:YES最大时钟频率:83.3 MHz
外部数据总线宽度:64格式:FLOATING POINT
集成缓存:YESJESD-30 代码:S-CBGA-X255
长度:21 mm低功率模式:YES
端子数量:255封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:CGA封装形状:SQUARE
封装形式:GRID ARRAY认证状态:Not Qualified
筛选级别:MIL-STD-883 Class B速度:233 MHz
最大供电电压:2.7 V最小供电电压:2.5 V
标称供电电压:2.6 V表面贴装:YES
技术:CMOS端子形式:UNSPECIFIED
端子节距:1.27 mm端子位置:BOTTOM
宽度:21 mmuPs/uCs/外围集成电路类型:MICROPROCESSOR, RISC
Base Number Matches:1

TSPC740AVGSB/Q10LH 数据手册

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TSPC750A/740A  
PowerPC750A/740A RISC MICROPROCESSOR Family  
Pid8t–750A/740A Specification  
.
DESCRIPTION  
The TSPC750A and TSPC740A microprocessor (after named  
750A/740A) are low–power implementations of the PowerPC  
Reduced Instruction Set Computer (RISC) architecture.  
The 750A/740A microprocessors designs are superscalar,  
capable of issuing three instructions per clock cycle into six  
independent execution units  
The 740A/750A microprocessors uses a 2,6/3,3–volts CMOS  
process technology and maintains full interface compatibility  
with TTL devices.  
The 750A/740A provides four software controlable power–  
saving modes and a thermal assist unit management.  
G suffix  
The 750A/740A microprocessors have separate 32–Kbyte,  
physically–addressed instruction and data caches and differ  
only in that the 750A features a dedicated L2 cache interface  
with on–chip L2 tags.  
CBGA255 and CBGA360  
Ceramic Ball Grid Array  
Both are software and bus–compatible with the PowerPC603  
and PowerPC604 families, and are fully JTAG compliant.  
The TSPC740A microprocessor is pin compatible with the  
TSPC603e family.  
MAIN FEATURES  
H 12.4SPECint95,8.4SPECfp95 @266Mhz (TSPC750A)  
w/1MB L2 @133Mhz  
H 11.5SPECint95,6.9SPECfp95 @266Mhz (TSPC740A)  
H 488 MIPS @ 266Mhz  
GS suffix  
H Selectable bus clock (11 CPU bus dividers up to 8x)  
H PD typical 4,2W @ 200Mhz, full operating conditions.  
H Nap, doze and sleep modes for power savings  
H Superscalar (3 instructions per clock cycle)  
H 4G–Byte direct addressing range.  
CI–CGA255 and CI–CGA360  
Ceramic Ball Grid Array  
with Solder Column Interposer (SCI)  
H 64–bit data and 32–bit address bus interface.  
H 32KB instruction and data cache.  
SCREENING  
This product is manufactured in full compliance wtih :  
H Six independent execution units and two register files.  
H Write–back and write–through operations.  
H fint max = 266Mhz  
HCBGA upscreenings based upon TCS standards  
HFull military temperature range (Tc=–55oC,+125oC)  
industrial temperature range (Tc=–40oC,+110oC)  
HCI–CGA versions of TSPC740A and TSPC750A (planned)  
H fbus max = 83,3Mhz  
HCI–CGA packages : MIL–STD–883 class Q or according to  
H Compatible CMOS input / TTL output  
TCS standards (planned)  
1/42  
March 2000  

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