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TSPC750ACCIP233EE PDF预览

TSPC750ACCIP233EE

更新时间: 2024-11-30 07:59:35
品牌 Logo 应用领域
爱特美尔 - ATMEL PC
页数 文件大小 规格书
17页 209K
描述
RISC Microprocessor, 32-Bit, 233MHz, CMOS, 2.54 MM PITCH, PCM, PGA-288

TSPC750ACCIP233EE 数据手册

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TSPC750IP  
Processor and Cache Module  
DESCRIPTION  
The Processor and Cache Module (PCM) is a 17 x 17 pin grid  
array (PGA) circuit assembly which combines a PowerPCt  
microprocessor and SRAM components into a CPU subsys-  
tem. The PCM provides a standard mechanical, electrical, and  
functional interface which can be socketed on a computer sys-  
tem board and allows many combinations of processors and  
optional components to be easily interchanged. This docu-  
ment describes the general characteristics for a module con-  
sisting of a single PowerPCt microprocessor and two SRAM  
devices for L2 cache. The PCM packaging and PGA signal  
definition also accomodates single processors without SRAM,  
and multiple processors.  
The PCM consists of an epoxy–glass (FR4) substrate which  
adapts a processor in a ceramic ball grid array (CBGA) pac-  
kage with 50 mil spacing to a 288–pin PGA with 100 mil spac-  
ing that can be easily socketed and hence, easily upgraded.  
The FR4 substrate can be extended beyond the area of the 17  
x 17 pin grid array to provide an interconnect area for SRAM  
components configured as closely coupled L2 cache. The  
resulting PCM provides numerous flexible configurations of  
processor and cache for various price/performance system  
designs.  
FR4 PCM on PGA 288 Interposer  
I
N
T
60x Address  
L2 Addr  
L2–Cache  
Memory  
Chips  
60x Data  
TSPC750  
L2 Data  
E
R
P
O
S
E
R
60x Control  
L2 Control  
Processor  
PLL_CFG  
P
I
N
S
General  
Support  
Circuits  
VID  
PID  
Simplified Block Diagram  
1/17  
April 1999  

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