Datasheet > TSPC603RMGSB/T12LC

TSPC603RMGSB/T12LC

更新时间： 2024-11-27 23:38:15

品牌	Logo	应用领域
其他 - ETC		外围集成电路时钟
页数	文件大小	规格书
42页	938K
描述
MICROPROCESSOR\|32-BIT\|CMOS\|BGA\|255PIN\|CERAMIC

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Features

• 7.4 SPECint95, 6.1 SPECfp95 @ 300 MHz (estimated)

• Superscalar (3 instructions per clock peak)

• Dual 16 KB Caches

• Selectable Bus Clock

• 32-bit Compatibility PowerPC Implementation

• On Chip Debug Support

• P_Dtypical = 3.5 Watts (266 MHz), Full Operating Conditions

• Nap, Doze and Sleep Modes for Power Savings

• Branch Folding

• 64-bit Data Bus (32-bit Data Bus Option)

• 4G byte Direct Addressing Range

• Pipelined Single/double Precision Float Unit

• IEEE 754 Compatible FPU

• IEEE P 1149-1 Test Mode (JTAG/C0P)

• f_intmax = 300 MHz

PowerPC

603e™ RISC

Microprocessor

Family

• f_busmax = 75 MHz

• Compatible CMOS Input / TTL Output

PID7t-603e

Specification

Screening / Quality / Packaging

This product is manufactured in full compliance with:

•

CI-CGA 255: MIL-STD-883 class Q or According to ATMEL-Grenoble standards

CBGA 255: Upscreenings based upon ATMEL-Grenoble standards

TSPC603R

Full Military Temperature Range (T_c= -55°C, T_c= +125°C)

IndustriaL Temperature Range (T_c= -40°C, T_c= +110°C)

•

Internal // I/O Power Supply = 2.5 ± 5% // 3.3V ± 5%

255 Pin CBGA Package and 255 Pin CBGA with SCI (CI-CGA) Package

Description

The PID7t-603e implementation of PowerPC603e (after named 603r) is a low-power

implementation of reduced instruction set computer (RISC) microprocessors Pow-

erPC family. The 603r implements 32-bit effective addresses, integer data types of

8, 16 and 32 bits, and floating-point data types of 32 and 64 bits.

The 603r is a low-power 2.5/3.3-volt design and provides four software controllable

power-saving modes.

The 603r is a superscalar processor capable of issuing and retiring as many as three

instructions per clock. Instructions can execute out of order for increased perfor-

mance; however, the 603r makes completion appear sequential. The 603r integrates

five execution units and is able to execute five instructions in parallel.

The 603r provides independent on-chip, 16K byte, four-way set-associative, physi-

cally addressed caches for instructions and data and on-chip instruction and data

memory management units (MMUs). The MMUs contain 64-entry, two-way set-asso-

ciative, data and instruction translation look aside buffers that provide support for

demand-paged virtual memory address translation and variable-sized block

translation.

The 603r has a selectable 32 or 64-bit data bus and a 32-bit address bus. The 603r

interface protocol allows multiple masters to complete for system resources through a

central external arbiter. The 603r supports single-beat and burst data transfers for

memory accesses, and supports memory-mapped I/O.

Rev. 2125A–12/01

12 3 4 5 6 7...42

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与TSPC603RMGSB/T12LC相关器件

型号	品牌	获取价格	描述	数据表
TSPC603RMGSB/T14LC	ETC	获取价格	MICROPROCESSOR\|32-BIT\|CMOS\|BGA\|255PIN\|CERAMIC
TSPC603RMGSB/T6L	ATMEL	获取价格	RISC Microprocessor, 32-Bit, 166MHz, CMOS, CBGA255,
TSPC603RMGSB/T6LC	ETC	获取价格	MICROPROCESSOR\|32-BIT\|CMOS\|BGA\|255PIN\|CERAMIC
TSPC603RMGSB/T8L	ATMEL	获取价格	RISC Microprocessor, 32-Bit, 200MHz, CMOS, CBGA255,
TSPC603RMGSB/T8LC	ETC	获取价格	MICROPROCESSOR\|32-BIT\|CMOS\|BGA\|255PIN\|CERAMIC
TSPC603RMGSU/T10LC	ETC	获取价格	MICROPROCESSOR\|32-BIT\|CMOS\|BGA\|255PIN\|CERAMIC
TSPC603RMGSU/T12LC	ETC	获取价格	MICROPROCESSOR\|32-BIT\|CMOS\|BGA\|255PIN\|CERAMIC
TSPC603RMGSU/T14LC	ETC	获取价格	MICROPROCESSOR\|32-BIT\|CMOS\|BGA\|255PIN\|CERAMIC
TSPC603RMGSU/T6LC	ETC	获取价格	MICROPROCESSOR\|32-BIT\|CMOS\|BGA\|255PIN\|CERAMIC
TSPC603RMGSU/T8LC	ETC	获取价格	MICROPROCESSOR\|32-BIT\|CMOS\|BGA\|255PIN\|CERAMIC

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